riscv/rocket-chip
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Chisel3: bulk connect is not commutative

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We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
This commit is contained in:
Andrew Waterman
2015-08-01 21:11:25 -07:00
parent 6c0e1e33ab
commit 52fc34a138
4 changed files with 34 additions and 32 deletions
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4
rocket/src/main/scala/icache.scala
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@ -93,7 +93,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
btb.io.ras_update := io.cpu.ras_update
btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate
tlb.io.ptw <> io.ptw
io.ptw <> tlb.io.ptw
tlb.io.req.valid := !stall && !icmiss
tlb.io.req.bits.vpn := s1_pc >> UInt(pgIdxBits)
tlb.io.req.bits.asid := UInt(0)
@ -101,7 +101,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
tlb.io.req.bits.instruction := Bool(true)
tlb.io.req.bits.store := Bool(false)
icache.io.mem <> io.mem
io.mem <> icache.io.mem
icache.io.req.valid := !stall && !s0_same_block
icache.io.req.bits.idx := io.cpu.npc
icache.io.invalidate := io.cpu.invalidate