riscv/rocket-chip
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Remove CSR back pressure ability

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We were using it for IPIs, but no longer need it.
This commit is contained in:
Andrew Waterman
2015-11-24 18:28:14 -08:00
parent 4616db4695
commit 5294e94794
2 changed files with 2 additions and 5 deletions
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3
rocket/src/main/scala/rocket.scala
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@ -364,8 +364,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
}
val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc
val replay_wb_common =
io.dmem.resp.bits.nack || wb_reg_replay || csr.io.csr_replay
val replay_wb_common = io.dmem.resp.bits.nack || wb_reg_replay
val wb_rocc_val = wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
val replay_wb = replay_wb_common || wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready
val wb_xcpt = wb_reg_xcpt || csr.io.csr_xcpt