From 5294e94794e351e7e58e992676d969c78478169b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 24 Nov 2015 18:28:14 -0800 Subject: [PATCH] Remove CSR back pressure ability We were using it for IPIs, but no longer need it. --- rocket/src/main/scala/csr.scala | 4 +--- rocket/src/main/scala/rocket.scala | 3 +-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index efaf25b8..c9675527 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -78,7 +78,6 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle { val wdata = Bits(INPUT, xLen) } - val csr_replay = Bool(OUTPUT) val csr_stall = Bool(OUTPUT) val csr_xcpt = Bool(OUTPUT) val eret = Bool(OUTPUT) @@ -347,14 +346,13 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) reg_sepc := reg_mepc } - assert(PopCount(insn_ret :: insn_redirect_trap :: io.exception :: csr_xcpt :: io.csr_replay :: Nil) <= 1, "these conditions must be mutually exclusive") + assert(PopCount(insn_ret :: insn_redirect_trap :: io.exception :: csr_xcpt :: Nil) <= 1, "these conditions must be mutually exclusive") when (read_time >= reg_mtimecmp) { reg_mip.mtip := true } io.time := reg_cycle - io.csr_replay := false io.csr_stall := reg_wfi when (host_csr_req_fire && !host_csr_bits.rw && decoded_addr(CSRs.mtohost)) { reg_tohost := UInt(0) } diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala index 2cabc403..53824d51 100644 --- a/rocket/src/main/scala/rocket.scala +++ b/rocket/src/main/scala/rocket.scala @@ -364,8 +364,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) { } val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc - val replay_wb_common = - io.dmem.resp.bits.nack || wb_reg_replay || csr.io.csr_replay + val replay_wb_common = io.dmem.resp.bits.nack || wb_reg_replay val wb_rocc_val = wb_reg_valid && wb_ctrl.rocc && !replay_wb_common val replay_wb = replay_wb_common || wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val wb_xcpt = wb_reg_xcpt || csr.io.csr_xcpt