riscv/rocket-chip
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actually use backendBuffering in front of unwrapper/converter chain

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Howard Mao 2015-11-09 11:50:08 -08:00
parent 1e772daeea
commit 51f128ec74
2 changed files with 2 additions and 2 deletions
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src/main/scala/RocketChip.scala
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@ -244,7 +244,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams)) val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost")) val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams)) val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
unwrap.io.in <> bank.outerTL unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)
narrow.io.in <> unwrap.io.out narrow.io.in <> unwrap.io.out
conv.io.tl <> narrow.io.out conv.io.tl <> narrow.io.out
TopUtils.connectNasti(interconnect.io.masters(i), conv.io.nasti) TopUtils.connectNasti(interconnect.io.masters(i), conv.io.nasti)

2
uncore

@ -1 +1 @@
Subproject commit b80bb3da5c201174cde361f1f384cf3725147e47 Subproject commit edf24e289d162bdd697fe31342b907123e7e82dd