diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 36c966d7..cdd43db9 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -244,7 +244,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
     val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
     val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
     val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
-    unwrap.io.in <> bank.outerTL
+    unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)
     narrow.io.in <> unwrap.io.out
     conv.io.tl <> narrow.io.out
     TopUtils.connectNasti(interconnect.io.masters(i), conv.io.nasti)
diff --git a/uncore b/uncore
index b80bb3da..edf24e28 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit b80bb3da5c201174cde361f1f384cf3725147e47
+Subproject commit edf24e289d162bdd697fe31342b907123e7e82dd