riscv/rocket-chip
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Separate I$ and D$ interface signals that span clock cycles

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For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
This commit is contained in:
Andrew Waterman
2016-04-01 19:30:39 -07:00
parent dc662f28a0
commit 51e0870e23
6 changed files with 52 additions and 48 deletions
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8
rocket/src/main/scala/ptw.scala
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@ -118,8 +118,8 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
io.mem.req.bits.cmd := Mux(state === s_set_dirty, M_XA_OR, M_XRD)
io.mem.req.bits.typ := MT_D
io.mem.req.bits.addr := pte_addr
io.mem.req.bits.kill := Bool(false)
io.mem.req.bits.data := pte_wdata.toBits
io.mem.s1_data := pte_wdata.toBits
io.mem.s1_kill := Bool(false)
val r_resp_ppn = io.mem.req.bits.addr >> pgIdxBits
val resp_ppn = Vec((0 until pgLevels-1).map(i => Cat(r_resp_ppn >> pgLevelBits*(pgLevels-i-1), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ r_resp_ppn)(count)
@ -152,7 +152,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
}
}
is (s_wait) {
when (io.mem.resp.bits.nack) {
when (io.mem.s2_nack) {
state := s_req
}
when (io.mem.resp.valid) {
@ -172,7 +172,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
}
}
is (s_wait_dirty) {
when (io.mem.resp.bits.nack) {
when (io.mem.s2_nack) {
state := s_set_dirty
}
when (io.mem.resp.valid) {