riscv/rocket-chip
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Remove IPI network

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This is now provided via MMIO.
This commit is contained in:
Andrew Waterman 2015-11-16 21:53:14 -08:00
parent 485f1b7bd7
commit 5195a5b891
4 changed files with 3 additions and 14 deletions
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2
rocket

@ -1 +1 @@
Subproject commit b120ba250cb5a9b1419396127bed508c67ef79ce
Subproject commit 4aa954799a0e47d2bc6709417d78856f0968a877

4
src/main/scala/RocketChip.scala
View File

@ -101,8 +101,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
tile.io.host.reset := Reg(next=Reg(next=hl.reset))
tile.io.host.csr.req <> Queue(hl.csr.req)
hl.csr.resp <> Queue(tile.io.host.csr.resp)
hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
hl.debug_stats_csr := tile.io.host.debug_stats_csr
}
@ -151,8 +149,6 @@ class Uncore(implicit val p: Parameters) extends Module
for (i <- 0 until nTiles) {
io.htif(i).reset := htif.io.cpu(i).reset
io.htif(i).id := htif.io.cpu(i).id
htif.io.cpu(i).ipi_req <> io.htif(i).ipi_req
io.htif(i).ipi_rep <> htif.io.cpu(i).ipi_rep
htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr
val csr_arb = Module(new SMIArbiter(2, xLen, csrAddrBits))

2
uncore

@ -1 +1 @@
Subproject commit 32ca8dd752785e0bb89826987f1f140fe5211f06
Subproject commit 71682bb8e4e3560337449ef5dbf54dcef7a8a155

9
vsrc/ZscaleTestHarness.v
View File

@ -25,14 +25,7 @@ module ZscaleTestHarness;
.io_host_csr_req_bits_data({dummy, 32'd0}),
.io_host_csr_resp_ready(1'b1),
.io_host_csr_resp_valid(csr_resp_valid),
.io_host_csr_resp_bits({dummy, csr_resp_bits}),
.io_host_ipi_req_ready(1'b1),
.io_host_ipi_req_valid(),
.io_host_ipi_req_bits(),
.io_host_ipi_rep_ready(),
.io_host_ipi_rep_valid(1'b0),
.io_host_ipi_rep_bits()
.io_host_csr_resp_bits({dummy, csr_resp_bits})
);
reg [1023:0] loadmem = 0;