riscv/rocket-chip
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Remove IPI network

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This is now provided via MMIO.
This commit is contained in:
Andrew Waterman
2015-11-16 21:53:14 -08:00
parent 485f1b7bd7
commit 5195a5b891
4 changed files with 3 additions and 14 deletions
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4
src/main/scala/RocketChip.scala
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@ -101,8 +101,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
tile.io.host.reset := Reg(next=Reg(next=hl.reset))
tile.io.host.csr.req <> Queue(hl.csr.req)
hl.csr.resp <> Queue(tile.io.host.csr.resp)
hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
hl.debug_stats_csr := tile.io.host.debug_stats_csr
}
@ -151,8 +149,6 @@ class Uncore(implicit val p: Parameters) extends Module
for (i <- 0 until nTiles) {
io.htif(i).reset := htif.io.cpu(i).reset
io.htif(i).id := htif.io.cpu(i).id
htif.io.cpu(i).ipi_req <> io.htif(i).ipi_req
io.htif(i).ipi_rep <> htif.io.cpu(i).ipi_rep
htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr
val csr_arb = Module(new SMIArbiter(2, xLen, csrAddrBits))