riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

only write out finish from tile 0 in groundtest

Browse Source
This commit is contained in:
Howard Mao 2016-05-03 13:09:22 -07:00
parent b95f095aca
commit 518d510622
1 changed files with 10 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
groundtest/src/main/scala/tile.scala
View File

@ -137,7 +137,7 @@ class GroundTestFinisher(implicit p: Parameters) extends TLModule()(p) {
} }
class GroundTestTile(id: Int, resetSignal: Bool) class GroundTestTile(id: Int, resetSignal: Bool)
(implicit val p: Parameters) extends Tile(resetSignal)(p) { (implicit val p: Parameters) extends Tile(resetSignal)(p) {
val test = p(BuildGroundTest)(id, dcacheParams) val test = p(BuildGroundTest)(id, dcacheParams)
@ -151,11 +151,14 @@ class GroundTestTile(id: Int, resetSignal: Bool)
ptw.io.requestors(0) <> test.io.ptw ptw.io.requestors(0) <> test.io.ptw
ptw.io.requestors(1) <> dcache.io.ptw ptw.io.requestors(1) <> dcache.io.ptw
val finisher = Module(new GroundTestFinisher) // Only Tile 0 needs to write tohost
finisher.io.finished := test.io.finished if (id == 0) {
val finisher = Module(new GroundTestFinisher)
finisher.io.finished := test.io.finished
val memArb = Module(new ClientUncachedTileLinkIOArbiter(2)) val memArb = Module(new ClientUncachedTileLinkIOArbiter(2))
memArb.io.in(0) <> test.io.mem memArb.io.in(0) <> test.io.mem
memArb.io.in(1) <> finisher.io.mem memArb.io.in(1) <> finisher.io.mem
io.uncached.head <> memArb.io.out io.uncached.head <> memArb.io.out
} else { io.uncached.head <> test.io.mem }
} }