riscv/rocket-chip
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commit vec=true

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Yunsup Lee 2013-01-22 20:24:17 -08:00
parent bb5c465bb3
commit 516a64f576
1 changed files with 1 additions and 1 deletions
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src/main/scala/RocketChip.scala
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@ -358,7 +358,7 @@ class Top extends Component {
val dc = DCacheConfig(128, 4, co, ntlb = 8, val dc = DCacheConfig(128, 4, co, ntlb = 8,
nmshr = 2, nrpq = 16, nsdq = 17) nmshr = 2, nrpq = 16, nsdq = 17)
val rc = RocketConfiguration(lnConf, co, ic, dc, val rc = RocketConfiguration(lnConf, co, ic, dc,
fpu = true, vec = false) fpu = true, vec = true)
val tileList = (0 until NTILES).map(r => new Tile(resetSignal = resetSigs(r))(rc)) val tileList = (0 until NTILES).map(r => new Tile(resetSignal = resetSigs(r))(rc))
val uncore = new Uncore(HTIF_WIDTH, tileList) val uncore = new Uncore(HTIF_WIDTH, tileList)