From 516a64f5760a2762bd35d9cbdfff22b3a99915f8 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 22 Jan 2013 20:24:17 -0800 Subject: [PATCH] commit vec=true --- src/main/scala/RocketChip.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 5b1c1167..85136080 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -358,7 +358,7 @@ class Top extends Component { val dc = DCacheConfig(128, 4, co, ntlb = 8, nmshr = 2, nrpq = 16, nsdq = 17) val rc = RocketConfiguration(lnConf, co, ic, dc, - fpu = true, vec = false) + fpu = true, vec = true) val tileList = (0 until NTILES).map(r => new Tile(resetSignal = resetSigs(r))(rc)) val uncore = new Uncore(HTIF_WIDTH, tileList)