riscv/rocket-chip
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Don't emit writeback state machine logic for scratchpad (#1127)

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Firrtl can't DCE it because it would require analyzing the state machine.
This commit is contained in:
Andrew Waterman 2017-11-22 18:40:02 -06:00 committed by GitHub
parent a8d573beeb
commit 5155eb6059
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 54 additions and 53 deletions
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3
src/main/scala/rocket/DCache.scala
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@ -558,6 +558,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val newCoh = Wire(init = probeNewCoh) val newCoh = Wire(init = probeNewCoh)
releaseWay := s2_probe_way releaseWay := s2_probe_way
if (!usingDataScratchpad) {
when (s2_victimize && s2_victim_dirty) { when (s2_victimize && s2_victim_dirty) {
assert(!(s2_valid && s2_hit_valid && !s2_data_error)) assert(!(s2_valid && s2_hit_valid && !s2_data_error))
release_state := s_voluntary_writeback release_state := s_voluntary_writeback
@ -602,7 +603,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (releaseDone) { release_state := s_probe_write_meta } when (releaseDone) { release_state := s_probe_write_meta }
} }
when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta)) { when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta)) {
if (edge.manager.anySupportAcquireT)
tl_out_c.bits := edge.Release(fromSource = 0.U, tl_out_c.bits := edge.Release(fromSource = 0.U,
toAddress = 0.U, toAddress = 0.U,
lgSize = lgCacheBlockBytes, lgSize = lgCacheBlockBytes,
@ -621,6 +621,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (tl_out_c.fire()) { accrued := next } when (tl_out_c.fire()) { accrued := next }
next next
} }
}
dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles
dataArb.io.in(2).bits.write := false dataArb.io.in(2).bits.write := false