diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
index e1daa23b..2565f3e8 100644
--- a/src/main/scala/rocket/DCache.scala
+++ b/src/main/scala/rocket/DCache.scala
@@ -558,68 +558,69 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val newCoh = Wire(init = probeNewCoh)
   releaseWay := s2_probe_way
 
-  when (s2_victimize && s2_victim_dirty) {
-    assert(!(s2_valid && s2_hit_valid && !s2_data_error))
-    release_state := s_voluntary_writeback
-    probe_bits.address := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB)) << idxLSB
-  }
-  when (s2_probe) {
-    val probeNack = Wire(init = true.B)
-    when (s2_meta_error) {
-      release_state := s_probe_retry
-    }.elsewhen (s2_prb_ack_data) {
-      release_state := s_probe_rep_dirty
-    }.elsewhen (s2_probe_state.isValid()) {
+  if (!usingDataScratchpad) {
+    when (s2_victimize && s2_victim_dirty) {
+      assert(!(s2_valid && s2_hit_valid && !s2_data_error))
+      release_state := s_voluntary_writeback
+      probe_bits.address := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB)) << idxLSB
+    }
+    when (s2_probe) {
+      val probeNack = Wire(init = true.B)
+      when (s2_meta_error) {
+        release_state := s_probe_retry
+      }.elsewhen (s2_prb_ack_data) {
+        release_state := s_probe_rep_dirty
+      }.elsewhen (s2_probe_state.isValid()) {
+        tl_out_c.valid := true
+        tl_out_c.bits := cleanReleaseMessage
+        release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean)
+      }.otherwise {
+        tl_out_c.valid := true
+        probeNack := !releaseDone
+        release_state := Mux(releaseDone, s_ready, s_probe_rep_miss)
+      }
+      when (probeNack) { s1_nack := true }
+    }
+    when (release_state === s_probe_retry) {
+      metaArb.io.in(6).valid := true
+      metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address)
+      when (metaArb.io.in(6).ready) {
+        release_state := s_ready
+        s1_probe := true
+      }
+    }
+    when (release_state === s_probe_rep_miss) {
+      tl_out_c.valid := true
+      when (releaseDone) { release_state := s_ready }
+    }
+    when (release_state === s_probe_rep_clean) {
       tl_out_c.valid := true
       tl_out_c.bits := cleanReleaseMessage
-      release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean)
-    }.otherwise {
-      tl_out_c.valid := true
-      probeNack := !releaseDone
-      release_state := Mux(releaseDone, s_ready, s_probe_rep_miss)
+      when (releaseDone) { release_state := s_probe_write_meta }
     }
-    when (probeNack) { s1_nack := true }
-  }
-  when (release_state === s_probe_retry) {
-    metaArb.io.in(6).valid := true
-    metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address)
-    when (metaArb.io.in(6).ready) {
-      release_state := s_ready
-      s1_probe := true
+    when (release_state === s_probe_rep_dirty) {
+      tl_out_c.bits := dirtyReleaseMessage
+      when (releaseDone) { release_state := s_probe_write_meta }
     }
-  }
-  when (release_state === s_probe_rep_miss) {
-    tl_out_c.valid := true
-    when (releaseDone) { release_state := s_ready }
-  }
-  when (release_state === s_probe_rep_clean) {
-    tl_out_c.valid := true
-    tl_out_c.bits := cleanReleaseMessage
-    when (releaseDone) { release_state := s_probe_write_meta }
-  }
-  when (release_state === s_probe_rep_dirty) {
-    tl_out_c.bits := dirtyReleaseMessage
-    when (releaseDone) { release_state := s_probe_write_meta }
-  }
-  when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta)) {
-    if (edge.manager.anySupportAcquireT)
+    when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta)) {
       tl_out_c.bits := edge.Release(fromSource = 0.U,
                                     toAddress = 0.U,
                                     lgSize = lgCacheBlockBytes,
                                     shrinkPermissions = s2_shrink_param,
                                     data = 0.U)._2
-    newCoh := voluntaryNewCoh
-    releaseWay := s2_victim_way
-    when (releaseDone) { release_state := s_voluntary_write_meta }
-    when (tl_out_c.fire() && c_first) { release_ack_wait := true }
-  }
-  tl_out_c.bits.address := probe_bits.address
-  tl_out_c.bits.data := s2_data_corrected
-  tl_out_c.bits.error := inWriteback && {
-    val accrued = Reg(Bool())
-    val next = writeback_data_uncorrectable || (accrued && !c_first)
-    when (tl_out_c.fire()) { accrued := next }
-    next
+      newCoh := voluntaryNewCoh
+      releaseWay := s2_victim_way
+      when (releaseDone) { release_state := s_voluntary_write_meta }
+      when (tl_out_c.fire() && c_first) { release_ack_wait := true }
+    }
+    tl_out_c.bits.address := probe_bits.address
+    tl_out_c.bits.data := s2_data_corrected
+    tl_out_c.bits.error := inWriteback && {
+      val accrued = Reg(Bool())
+      val next = writeback_data_uncorrectable || (accrued && !c_first)
+      when (tl_out_c.fire()) { accrued := next }
+      next
+    }
   }
 
   dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles