riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Fix valid signal for multibeat grants

Browse Source
This commit is contained in:
Albert Ou 2016-06-08 15:13:39 -07:00
parent f421e2ab11
commit 5151570894
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
uncore/src/main/scala/bram.scala
View File

@ -23,7 +23,9 @@ class BRAMSlave(depth: Int)(implicit val p: Parameters) extends Module
multibeat := s0_getblk multibeat := s0_getblk
} }
val s0_valid = io.acquire.valid || multibeat
val last = Wire(Bool())
val s0_valid = io.acquire.valid || (multibeat && !last)
val s1_valid = Reg(next = s0_valid, init = Bool(false)) val s1_valid = Reg(next = s0_valid, init = Bool(false))
val s1_acq = RegEnable(io.acquire.bits, fire_acq) val s1_acq = RegEnable(io.acquire.bits, fire_acq)
@ -32,7 +34,7 @@ class BRAMSlave(depth: Int)(implicit val p: Parameters) extends Module
val s1_addr = Cat(s1_acq.addr_block, s1_beat) val s1_addr = Cat(s1_acq.addr_block, s1_beat)
val raddr = Mux(multibeat, s1_addr, s0_addr) val raddr = Mux(multibeat, s1_addr, s0_addr)
val last = (s1_acq.addr_beat === UInt(tlDataBeats-1)) last := (s1_acq.addr_beat === UInt(tlDataBeats-1))
val ren = (io.acquire.valid && (s0_get || s0_getblk)) || (multibeat && !last) val ren = (io.acquire.valid && (s0_get || s0_getblk)) || (multibeat && !last)
val wen = (io.acquire.valid && (s0_put || s0_putblk)) val wen = (io.acquire.valid && (s0_put || s0_putblk))