riscv/rocket-chip
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Flush blocking D$ on FENCE.I

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This commit is contained in:
Andrew Waterman
2016-05-31 19:27:28 -07:00
parent 3ee5144923
commit 51379621d6
4 changed files with 268 additions and 223 deletions
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rocket/src/main/scala/rocket.scala
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@ -509,7 +509,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret
Mux(replay_wb, wb_reg_pc, // replay
mem_npc)).toUInt // mispredicted branch
io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i
io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack
io.imem.flush_tlb := csr.io.fatc
io.imem.resp.ready := !ctrl_stalld || csr.io.interrupt || take_pc_mem