riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Flush blocking D$ on FENCE.I

Browse Source
This commit is contained in:
Andrew Waterman
2016-05-31 19:27:28 -07:00
parent 3ee5144923
commit 51379621d6
4 changed files with 268 additions and 223 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/nbdcache.scala
View File

@ -410,7 +410,7 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
when (!io.meta_read.ready) {
rpq.io.deq.ready := Bool(false)
io.replay.bits.cmd := M_NOP
io.replay.bits.cmd := M_FLUSH_ALL /* nop */
}
}
@ -800,7 +800,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
val s2_req = Reg(io.cpu.req.bits)
val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd =/= M_NOP
val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd =/= M_FLUSH_ALL
val s2_recycle = Wire(Bool())
val s2_valid_masked = Wire(Bool())