util: dontTouch work-around for zero width aggregates

src/main/scala/util/Misc.scala

@@ -4,7 +4,7 @@
 package freechips.rocketchip.util
 
 import Chisel._
-import chisel3.experimental.{dontTouch, RawModule}
+import chisel3.experimental.{ChiselAnnotation, RawModule}
 import freechips.rocketchip.config.Parameters
 import scala.math._
 
@@ -26,6 +26,13 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle {
 trait DontTouch {
   self: RawModule =>
 
+  def dontTouch(data: Data): Unit = data match {
+    case agg: Aggregate =>
+      agg.getElements.foreach(dontTouch)
+    case elt: Element =>
+      annotate(ChiselAnnotation(elt, classOf[firrtl.Transform], "DONTtouch!"))
+  }
+
   /** Marks every port as don't touch
     *
     * @note This method can only be called after the Module has been fully constructed