riscv/rocket-chip
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Fix MIF bug that cuts off upper xact id bits

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This commit is contained in:
Eric Love
2016-03-11 16:59:24 -08:00
committed by Howard Mao
parent 9dc0cbdfa4
commit 4fc2a14a63
3 changed files with 8 additions and 3 deletions
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2
junctions

Submodule junctions updated: aa67573876...b0fa161f60

7
src/main/scala/Configs.scala
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@@ -73,10 +73,15 @@ class DefaultConfig extends Config (
case ASIdBits => 7 case ASIdBits => 7
case MIFTagBits => Dump("MIF_TAG_BITS", case MIFTagBits => Dump("MIF_TAG_BITS",
// Bits needed at the L2 agent // Bits needed at the L2 agent
log2Up(site(NAcquireTransactors)+2) + site(MIFMasterTagBits) +
// Bits added by NASTI interconnect // Bits added by NASTI interconnect
max(log2Up(site(MaxBanksPerMemoryChannel)), max(log2Up(site(MaxBanksPerMemoryChannel)),
(if (site(UseDma)) 3 else 2))) (if (site(UseDma)) 3 else 2)))
case MIFMasterTagBits => log2Up(max(
site(NTiles),
max(
site(NAcquireTransactors)+2,
site(NDmaTransactors))))
case MIFDataBits => Dump("MIF_DATA_BITS", 64) case MIFDataBits => Dump("MIF_DATA_BITS", 64)
case MIFAddrBits => Dump("MIF_ADDR_BITS", case MIFAddrBits => Dump("MIF_ADDR_BITS",
site(PAddrBits) - site(CacheBlockOffsetBits)) site(PAddrBits) - site(CacheBlockOffsetBits))

2
uncore

Submodule uncore updated: 2e2e297ee7...9d4a38e955