riscv/rocket-chip
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split the isa tests properly

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Howard Mao committed 2016-06-22 16:14:02 -07:00
1 parent 5edb448a1f
commit 4fbe7d6cf7
3 files changed
+31 -21
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src/main/scala/Configs.scala
+8 -2
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@@ -216,8 +216,14 @@ class BaseConfig extends Config (
case XLen => 64
case UseFPU => {
val env = if(site(UseVM)) List("p","v") else List("p")
if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
else TestGeneration.addSuites(env.map(rv64ufNoDiv))
if(site(FDivSqrt)) {
TestGeneration.addSuites(env.map(rv64uf))
TestGeneration.addSuites(env.map(rv64ud))
}
else {
TestGeneration.addSuites(env.map(rv64ufNoDiv))
TestGeneration.addSuites(env.map(rv64udNoDiv))
}
true
}
case UseAtomics => {