diff --git a/riscv-tools b/riscv-tools index ba7efc42..5a79333c 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit ba7efc42d04bcd1dacd8545acba58894aacc8c9e +Subproject commit 5a79333c1c559bbaeedfd6e57bdcd8797558f616 diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 73234af0..f44b91c6 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -216,8 +216,14 @@ class BaseConfig extends Config ( case XLen => 64 case UseFPU => { val env = if(site(UseVM)) List("p","v") else List("p") - if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf)) - else TestGeneration.addSuites(env.map(rv64ufNoDiv)) + if(site(FDivSqrt)) { + TestGeneration.addSuites(env.map(rv64uf)) + TestGeneration.addSuites(env.map(rv64ud)) + } + else { + TestGeneration.addSuites(env.map(rv64ufNoDiv)) + TestGeneration.addSuites(env.map(rv64udNoDiv)) + } true } case UseAtomics => { diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala index 01e56c82..c76e625e 100644 --- a/src/main/scala/Testing.scala +++ b/src/main/scala/Testing.scala @@ -30,10 +30,10 @@ run-$makeTargetName-debug: $$(addprefix $$(output_dir)/, $$(addsuffix .vpd, $$($ """ } -class AssemblyTestSuite(makePrefix: String, toolsPrefix: String, val names: LinkedHashSet[String])(val envName: String) extends RocketTestSuite { +class AssemblyTestSuite(prefix: String, val names: LinkedHashSet[String])(val envName: String) extends RocketTestSuite { val dir = "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa" - val makeTargetName = makePrefix + "-" + envName + "-asm-tests" - override def toString = s"$makeTargetName = \\\n" + names.map(n => s"\t$toolsPrefix-$envName-$n").mkString(" \\\n") + postScript + val makeTargetName = prefix + "-" + envName + "-asm-tests" + override def toString = s"$makeTargetName = \\\n" + names.map(n => s"\t$prefix-$envName-$n").mkString(" \\\n") + postScript } class BenchmarkTestSuite(makePrefix: String, val dir: String, val names: LinkedHashSet[String]) extends RocketTestSuite { @@ -98,45 +98,49 @@ object DefaultTestSuites { "simple", "add", "addi", "and", "andi", "auipc", "beq", "bge", "bgeu", "blt", "bltu", "bne", "fence_i", "j", "jal", "jalr", "lb", "lbu", "lh", "lhu", "lui", "lw", "or", "ori", "sb", "sh", "sw", "sll", "slli", "slt", "slti", "sra", "srai", "srl", "srli", "sub", "xor", "xori") - val rv32ui = new AssemblyTestSuite("rv32ui", "rv32ui", rv32uiNames)(_) + val rv32ui = new AssemblyTestSuite("rv32ui", rv32uiNames)(_) val rv32umNames = LinkedHashSet("mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu") - val rv32um = new AssemblyTestSuite("rv32um", "rv32ui", rv32umNames)(_) + val rv32um = new AssemblyTestSuite("rv32um", rv32umNames)(_) val rv32uaNames = LinkedHashSet("lrsc", "amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w") - val rv32ua = new AssemblyTestSuite("rv32ua", "rv32ui", rv32uaNames)(_) + val rv32ua = new AssemblyTestSuite("rv32ua", rv32uaNames)(_) val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi") - val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_) + val rv32si = new AssemblyTestSuite("rv32si", rv32siNames)(_) val rv32miNames = LinkedHashSet("breakpoint", "csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall") - val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_) + val rv32mi = new AssemblyTestSuite("rv32mi", rv32miNames)(_) val rv32u = List(rv32ui, rv32um) val rv32i = List(rv32ui, rv32si, rv32mi) val rv64uiNames = LinkedHashSet("addw", "addiw", "ld", "lwu", "sd", "slliw", "sllw", "sltiu", "sltu", "sraiw", "sraw", "srliw", "srlw", "subw") - val rv64ui = new AssemblyTestSuite("rv64ui", "rv64ui", rv32uiNames ++ rv64uiNames)(_) + val rv64ui = new AssemblyTestSuite("rv64ui", rv32uiNames ++ rv64uiNames)(_) val rv64umNames = LinkedHashSet("divuw", "divw", "mulw", "remuw", "remw") - val rv64um = new AssemblyTestSuite("rv64um", "rv64ui", rv32umNames ++ rv64umNames)(_) + val rv64um = new AssemblyTestSuite("rv64um", rv32umNames ++ rv64umNames)(_) val rv64uaNames = rv32uaNames.map(_.replaceAll("_w","_d")) - val rv64ua = new AssemblyTestSuite("rv64ua", "rv64ui", rv32uaNames ++ rv64uaNames)(_) + val rv64ua = new AssemblyTestSuite("rv64ua", rv32uaNames ++ rv64uaNames)(_) - val rv64ufNames = LinkedHashSet("ldst", "move", "fsgnj", "fcmp", "fcvt", "fcvt_w", "fclass", "fadd", "fdiv", "fmin", "fmadd", "structural") - val rv64uf = new AssemblyTestSuite("rv64uf", "rv64uf", rv64ufNames)(_) - val rv64ufNoDiv = new AssemblyTestSuite("rv64uf", "rv64uf", rv64ufNames - "fdiv")(_) + val rv64ufNames = LinkedHashSet("ldst", "move", "fsgnj", "fcmp", "fcvt", "fcvt_w", "fclass", "fadd", "fdiv", "fmin", "fmadd") + val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_) + val rv64ufNoDiv = new AssemblyTestSuite("rv64uf", rv64ufNames - "fdiv")(_) + + val rv64udNames = rv64ufNames + "structural" + val rv64ud = new AssemblyTestSuite("rv64ud", rv64udNames)(_) + val rv64udNoDiv = new AssemblyTestSuite("rv64ud", rv64udNames - "fdiv")(_) val rv64siNames = rv32siNames - val rv64si = new AssemblyTestSuite("rv64si", "rv64si", rv64siNames)(_) + val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_) val rv64miNames = rv32miNames - val rv64mi = new AssemblyTestSuite("rv64mi", "rv64mi", rv64miNames)(_) + val rv64mi = new AssemblyTestSuite("rv64mi", rv64miNames)(_) val groundtestNames = LinkedHashSet("simple") - val groundtest64 = new AssemblyTestSuite("groundtest", "rv64ui", groundtestNames)(_) - val groundtest32 = new AssemblyTestSuite("groundtest", "rv32ui", groundtestNames)(_) + val groundtest64 = new AssemblyTestSuite("rv64ui", groundtestNames)(_) + val groundtest32 = new AssemblyTestSuite("rv32ui", groundtestNames)(_) // TODO: "rv64ui-pm-lrsc", "rv64mi-pm-ipi",