add memtest config for testing memory channel mux
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@ -219,7 +219,7 @@ class DefaultConfig extends Config (
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
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maxClientXacts = site(NAcquireTransactors) + 2,
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maxClientsPerPort = site(NBanksPerMemoryChannel),
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maxClientsPerPort = site(MaxBanksPerMemoryChannel),
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dataBeats = site(MIFDataBeats))
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case TLKey("L2toMMIO") => {
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val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase))
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@ -144,3 +144,7 @@ class TraceGenConfig extends Config(new With2Cores ++ new WithL2Cache ++ new Wit
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class FancyMemtestConfig extends Config(
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new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++
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new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
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class MemoryMuxMemtestConfig extends Config(
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new With2MemoryChannels ++ new WithOneOrMaxChannels ++
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new WithMemtest ++ new GroundTestConfig)
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