From 4f06a5ff6b84219258a7312fd2c6d8a122a7b110 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 31 Mar 2016 18:40:35 -0700 Subject: [PATCH] add memtest config for testing memory channel mux --- src/main/scala/Configs.scala | 2 +- src/main/scala/TestConfigs.scala | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index f54d5f83..24d637b1 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -219,7 +219,7 @@ class DefaultConfig extends Config ( dataBits = site(CacheBlockBytes)*8) case TLKey("Outermost") => site(TLKey("L2toMC")).copy( maxClientXacts = site(NAcquireTransactors) + 2, - maxClientsPerPort = site(NBanksPerMemoryChannel), + maxClientsPerPort = site(MaxBanksPerMemoryChannel), dataBeats = site(MIFDataBeats)) case TLKey("L2toMMIO") => { val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase)) diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala index 29239897..869e4b66 100644 --- a/src/main/scala/TestConfigs.scala +++ b/src/main/scala/TestConfigs.scala @@ -144,3 +144,7 @@ class TraceGenConfig extends Config(new With2Cores ++ new WithL2Cache ++ new Wit class FancyMemtestConfig extends Config( new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++ new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig) + +class MemoryMuxMemtestConfig extends Config( + new With2MemoryChannels ++ new WithOneOrMaxChannels ++ + new WithMemtest ++ new GroundTestConfig)