riscv/rocket-chip
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add memtest config for testing memory channel mux

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This commit is contained in:
Howard Mao
2016-03-31 18:40:35 -07:00
parent 5a74a9b1e7
commit 4f06a5ff6b
2 changed files with 5 additions and 1 deletions
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src/main/scala/Configs.scala
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@ -219,7 +219,7 @@ class DefaultConfig extends Config (
dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
maxClientXacts = site(NAcquireTransactors) + 2,
maxClientsPerPort = site(NBanksPerMemoryChannel),
maxClientsPerPort = site(MaxBanksPerMemoryChannel),
dataBeats = site(MIFDataBeats))
case TLKey("L2toMMIO") => {
val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase))