riscv/rocket-chip
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update to new chisel/hwacha

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This commit is contained in:
Andrew Waterman 2012-06-08 00:13:14 -07:00
parent a99cebb483
commit 4e5f874266
3 changed files with 7 additions and 7 deletions
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6
rocket/src/main/scala/fpu.scala
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@ -467,9 +467,9 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
val regfile = Mem(32) { Bits(width = 65) } val regfile = Mem(32) { Bits(width = 65) }
when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded } when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded }
val ex_rs1 = regfile.read(ex_reg_inst(26,22)) val ex_rs1 = regfile(ex_reg_inst(26,22))
val ex_rs2 = regfile.read(ex_reg_inst(21,17)) val ex_rs2 = regfile(ex_reg_inst(21,17))
val ex_rs3 = regfile.read(ex_reg_inst(16,12)) val ex_rs3 = regfile(ex_reg_inst(16,12))
val ex_rm = Mux(ex_reg_inst(11,9) === Bits(7), fsr_rm, ex_reg_inst(11,9)) val ex_rm = Mux(ex_reg_inst(11,9) === Bits(7), fsr_rm, ex_reg_inst(11,9))
val mem_reg_valid = Reg(ex_reg_valid && !io.ctrl.killx, resetVal = Bool(false)) val mem_reg_valid = Reg(ex_reg_valid && !io.ctrl.killx, resetVal = Bool(false))

4
rocket/src/main/scala/icache.scala
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@ -97,7 +97,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
for (i <- 0 until assoc) for (i <- 0 until assoc)
{ {
val repl_me = (repl_way === UFix(i)) val repl_me = (repl_way === UFix(i))
val tag_array = Mem(sets){ Bits(width = tagbits) } val tag_array = Mem(sets, seqRead = true){ Bits(width = tagbits) }
val tag_rdata = Reg() { Bits(width = tagbits) } val tag_rdata = Reg() { Bits(width = tagbits) }
when (tag_we && repl_me) { tag_array(tag_addr) := r_cpu_miss_tag } when (tag_we && repl_me) { tag_array(tag_addr) := r_cpu_miss_tag }
.otherwise { tag_rdata := tag_array(tag_addr) } .otherwise { tag_rdata := tag_array(tag_addr) }
@ -115,7 +115,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb)) val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb))
// data array // data array
val data_array = Mem(sets*REFILL_CYCLES){ io.mem.xact_rep.bits.data.clone } val data_array = Mem(sets*REFILL_CYCLES, seqRead = true){ io.mem.xact_rep.bits.data.clone }
val data_out = Reg(){ io.mem.xact_rep.bits.data.clone } val data_out = Reg(){ io.mem.xact_rep.bits.data.clone }
when (io.mem.xact_rep.valid && repl_me) { data_array(data_addr) := io.mem.xact_rep.bits.data } when (io.mem.xact_rep.valid && repl_me) { data_array(data_addr) := io.mem.xact_rep.bits.data }
.otherwise { data_out := data_array(data_addr) } .otherwise { data_out := data_array(data_addr) }

4
rocket/src/main/scala/nbdcache.scala
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@ -612,7 +612,7 @@ class MetaDataArray(lines: Int) extends Component {
.otherwise { raddr := io.req.bits.idx } .otherwise { raddr := io.req.bits.idx }
} }
val tag_array = Mem(lines){ Bits(width=TAG_BITS) } val tag_array = Mem(lines, seqRead = true){ Bits(width=TAG_BITS) }
val tag_rdata = Reg() { Bits() } val tag_rdata = Reg() { Bits() }
when (io.req.valid) { when (io.req.valid) {
when (io.req.bits.rw) { tag_array(io.req.bits.idx) := io.req.bits.data.tag } when (io.req.bits.rw) { tag_array(io.req.bits.idx) := io.req.bits.data.tag }
@ -661,7 +661,7 @@ class DataArray(lines: Int) extends Component {
val addr = Cat(io.req.bits.idx, io.req.bits.offset) val addr = Cat(io.req.bits.idx, io.req.bits.offset)
val rdata = Reg() { Bits() } val rdata = Reg() { Bits() }
val array = Mem(lines*REFILL_CYCLES){ Bits(width=MEM_DATA_BITS) } val array = Mem(lines*REFILL_CYCLES, seqRead = true){ Bits(width=MEM_DATA_BITS) }
when (io.req.valid) { when (io.req.valid) {
when (io.req.bits.rw) { array.write(addr, io.req.bits.data, wmask) } when (io.req.bits.rw) { array.write(addr, io.req.bits.data, wmask) }
.otherwise { rdata := array(addr) } .otherwise { rdata := array(addr) }