riscv/rocket-chip
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update to new chisel/hwacha

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This commit is contained in:
Andrew Waterman
2012-06-08 00:13:14 -07:00
parent a99cebb483
commit 4e5f874266
3 changed files with 7 additions and 7 deletions
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4
rocket/src/main/scala/nbdcache.scala
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@ -612,7 +612,7 @@ class MetaDataArray(lines: Int) extends Component {
.otherwise { raddr := io.req.bits.idx }
}
val tag_array = Mem(lines){ Bits(width=TAG_BITS) }
val tag_array = Mem(lines, seqRead = true){ Bits(width=TAG_BITS) }
val tag_rdata = Reg() { Bits() }
when (io.req.valid) {
when (io.req.bits.rw) { tag_array(io.req.bits.idx) := io.req.bits.data.tag }
@ -661,7 +661,7 @@ class DataArray(lines: Int) extends Component {
val addr = Cat(io.req.bits.idx, io.req.bits.offset)
val rdata = Reg() { Bits() }
val array = Mem(lines*REFILL_CYCLES){ Bits(width=MEM_DATA_BITS) }
val array = Mem(lines*REFILL_CYCLES, seqRead = true){ Bits(width=MEM_DATA_BITS) }
when (io.req.valid) {
when (io.req.bits.rw) { array.write(addr, io.req.bits.data, wmask) }
.otherwise { rdata := array(addr) }