riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

update to new chisel/hwacha

Browse Source
This commit is contained in:
Andrew Waterman
2012-06-08 00:13:14 -07:00
parent a99cebb483
commit 4e5f874266
3 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/icache.scala
View File

@ -97,7 +97,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
for (i <- 0 until assoc)
{
val repl_me = (repl_way === UFix(i))
val tag_array = Mem(sets){ Bits(width = tagbits) }
val tag_array = Mem(sets, seqRead = true){ Bits(width = tagbits) }
val tag_rdata = Reg() { Bits(width = tagbits) }
when (tag_we && repl_me) { tag_array(tag_addr) := r_cpu_miss_tag }
.otherwise { tag_rdata := tag_array(tag_addr) }
@ -115,7 +115,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb))
// data array
val data_array = Mem(sets*REFILL_CYCLES){ io.mem.xact_rep.bits.data.clone }
val data_array = Mem(sets*REFILL_CYCLES, seqRead = true){ io.mem.xact_rep.bits.data.clone }
val data_out = Reg(){ io.mem.xact_rep.bits.data.clone }
when (io.mem.xact_rep.valid && repl_me) { data_array(data_addr) := io.mem.xact_rep.bits.data }
.otherwise { data_out := data_array(data_addr) }