riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

update to new chisel/hwacha

Browse Source
This commit is contained in:
Andrew Waterman
2012-06-08 00:13:14 -07:00
parent a99cebb483
commit 4e5f874266
3 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
rocket/src/main/scala/fpu.scala
View File

@ -467,9 +467,9 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
val regfile = Mem(32) { Bits(width = 65) }
when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded }
val ex_rs1 = regfile.read(ex_reg_inst(26,22))
val ex_rs2 = regfile.read(ex_reg_inst(21,17))
val ex_rs3 = regfile.read(ex_reg_inst(16,12))
val ex_rs1 = regfile(ex_reg_inst(26,22))
val ex_rs2 = regfile(ex_reg_inst(21,17))
val ex_rs3 = regfile(ex_reg_inst(16,12))
val ex_rm = Mux(ex_reg_inst(11,9) === Bits(7), fsr_rm, ex_reg_inst(11,9))
val mem_reg_valid = Reg(ex_reg_valid && !io.ctrl.killx, resetVal = Bool(false))