riscv/rocket-chip
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add new parameters for new SCR file

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John Wright 2016-02-12 18:24:12 -08:00
parent 9fb2216548
commit 4dad5b8b32
2 changed files with 3 additions and 0 deletions
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2
src/main/scala/Configs.scala
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@ -75,9 +75,11 @@ class DefaultConfig extends Config (
case HtifKey => HtifParameters( case HtifKey => HtifParameters(
width = Dump("HTIF_WIDTH", 16), width = Dump("HTIF_WIDTH", 16),
nSCR = 64, nSCR = 64,
nUncoreSCR = 64,
csrDataBits = site(XLen), csrDataBits = site(XLen),
offsetBits = site(CacheBlockOffsetBits), offsetBits = site(CacheBlockOffsetBits),
nCores = site(NTiles)) nCores = site(NTiles))
case GlobalScrMap => new ScrMap
//Memory Parameters //Memory Parameters
case PAddrBits => 32 case PAddrBits => 32
case PgIdxBits => 12 case PgIdxBits => 12

1
src/main/scala/RocketChip.scala
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@ -53,6 +53,7 @@ trait HasTopLevelParameters {
lazy val mifDataBeats = p(MIFDataBeats) lazy val mifDataBeats = p(MIFDataBeats)
lazy val xLen = p(XLen) lazy val xLen = p(XLen)
lazy val nSCR = p(HtifKey).nSCR lazy val nSCR = p(HtifKey).nSCR
lazy val nUncoreSCR = p(HtifKey).nUncoreSCR
lazy val scrAddrBits = log2Up(nSCR) lazy val scrAddrBits = log2Up(nSCR)
lazy val scrDataBits = 64 lazy val scrDataBits = 64
lazy val scrDataBytes = scrDataBits / 8 lazy val scrDataBytes = scrDataBits / 8