From 4dad5b8b32dac06601cfff1d048eadcc30a8873b Mon Sep 17 00:00:00 2001
From: John Wright <johnwright@eecs.berkeley.edu>
Date: Fri, 12 Feb 2016 18:24:12 -0800
Subject: [PATCH] add new parameters for new SCR file

---
 src/main/scala/Configs.scala    | 2 ++
 src/main/scala/RocketChip.scala | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index a0b66f30..60ef62a4 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -75,9 +75,11 @@ class DefaultConfig extends Config (
       case HtifKey => HtifParameters(
                        width = Dump("HTIF_WIDTH", 16),
                        nSCR = 64,
+                       nUncoreSCR = 64,
                        csrDataBits = site(XLen),
                        offsetBits = site(CacheBlockOffsetBits),
                        nCores = site(NTiles))
+      case GlobalScrMap => new ScrMap
       //Memory Parameters
       case PAddrBits => 32
       case PgIdxBits => 12
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 3e1efeaf..fbcb2d51 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -53,6 +53,7 @@ trait HasTopLevelParameters {
   lazy val mifDataBeats = p(MIFDataBeats)
   lazy val xLen = p(XLen)
   lazy val nSCR =  p(HtifKey).nSCR
+  lazy val nUncoreSCR = p(HtifKey).nUncoreSCR
   lazy val scrAddrBits = log2Up(nSCR)
   lazy val scrDataBits = 64
   lazy val scrDataBytes = scrDataBits / 8