riscv/rocket-chip
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revamp vector yet again with new D$

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Yunsup Lee committed 2012-11-18 03:14:22 -08:00
1 parent 7bcf59a18f
commit 4d73e6e38a
3 files changed
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riscv-rocket
+1 -1
Submodule riscv-rocket updated: 238b637fb2...b8858dc32c.
src/main/scala/RocketChip.scala
+1 -1
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@@ -211,7 +211,7 @@ class Top extends Component {
val dc = DCacheConfig(128, 4, co, val dc = DCacheConfig(128, 4, co,
nmshr = 2, nrpq = 16, nsdq = 17) nmshr = 2, nrpq = 16, nsdq = 17)
val rc = RocketConfiguration(NTILES, co, ic, dc, val rc = RocketConfiguration(NTILES, co, ic, dc,
fpu = true, vec = false) fpu = true, vec = true)
val tile = new Tile(resetSignal = hl.reset)(rc) val tile = new Tile(resetSignal = hl.reset)(rc)
tile.io.host.reset := Reg(Reg(hl.reset)) tile.io.host.reset := Reg(Reg(hl.reset))
uncore
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Submodule uncore updated: 904c136aa9...80cdd7deed.