From 4d73e6e38a0c51a009fa22e8c6214d7b3e0cacb8 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sun, 18 Nov 2012 03:14:22 -0800 Subject: [PATCH] revamp vector yet again with new D$ --- riscv-rocket | 2 +- src/main/scala/RocketChip.scala | 2 +- uncore | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv-rocket b/riscv-rocket index 238b637f..b8858dc3 160000 --- a/riscv-rocket +++ b/riscv-rocket @@ -1 +1 @@ -Subproject commit 238b637fb2bad9da4c935993dc937523fdf5938b +Subproject commit b8858dc32c0efd20f94a717f49930f62b565ab1c diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index cfad0a3a..1c14934f 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -211,7 +211,7 @@ class Top extends Component { val dc = DCacheConfig(128, 4, co, nmshr = 2, nrpq = 16, nsdq = 17) val rc = RocketConfiguration(NTILES, co, ic, dc, - fpu = true, vec = false) + fpu = true, vec = true) val tile = new Tile(resetSignal = hl.reset)(rc) tile.io.host.reset := Reg(Reg(hl.reset)) diff --git a/uncore b/uncore index 904c136a..80cdd7de 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 904c136aa9d80b433ed16067d05124cabed933c1 +Subproject commit 80cdd7deedc148852173aed1155484ae2146bb66