riscv/rocket-chip
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Added assert to nbdcache

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This commit is contained in:
Christopher Celio 2015-04-11 02:58:34 -07:00
parent a564f08702
commit 4d6ebded02
1 changed files with 4 additions and 0 deletions
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4
rocket/src/main/scala/nbdcache.scala
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@ -686,6 +686,10 @@ class HellaCache extends L1HellaCacheModule {
io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld
io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st
assert (!(Reg(next=
(io.cpu.xcpt.ma.ld || io.cpu.xcpt.ma.st || io.cpu.xcpt.pf.ld || io.cpu.xcpt.pf.st)) &&
io.cpu.resp.valid), "DCache exception occurred - cache response not killed.")
// tags // tags
def onReset = L1Metadata(UInt(0), ClientMetadata.onReset) def onReset = L1Metadata(UInt(0), ClientMetadata.onReset)
val meta = Module(new MetadataArray(onReset _)) val meta = Module(new MetadataArray(onReset _))