riscv/rocket-chip
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Add instruction-trace port

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This commit is contained in:
Andrew Waterman
2017-09-19 22:59:28 -07:00
parent acea94bcef
commit 4d6d6ff641
7 changed files with 62 additions and 33 deletions
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5
src/main/scala/tile/RocketTile.scala
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@ -19,6 +19,7 @@ case class RocketTileParams(
btb: Option[BTBParams] = Some(BTBParams()),
dataScratchpadBytes: Int = 0,
boundaryBuffers: Boolean = false,
trace: Boolean = false,
name: Option[String] = Some("tile"),
externalMasterBuffers: Int = 0,
externalSlaveBuffers: Int = 0) extends TileParams {
@ -139,6 +140,7 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
val core = Module(p(BuildCore)(outer.p))
decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
core.io.hartid := io.hartid // Pass through the hartid
io.trace.foreach { _ := core.io.trace }
outer.frontend.module.io.cpu <> core.io.imem
outer.frontend.module.io.reset_vector := io.reset_vector
outer.frontend.module.io.hartid := io.hartid
@ -196,7 +198,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
}
lazy val module = new LazyModuleImp(this) {
val io = new CoreBundle with HasExternallyDrivenTileConstants {
val io = new CoreBundle with HasExternallyDrivenTileConstants with CanHaveInstructionTracePort {
val master = masterNode.bundleOut
val slave = slaveNode.bundleIn
val asyncInterrupts = asyncIntNode.bundleIn
@ -206,6 +208,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
// signals that do not change based on crossing type:
rocket.module.io.hartid := io.hartid
rocket.module.io.reset_vector := io.reset_vector
io.trace.foreach { _ := rocket.module.io.trace.get }
}
}