riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Add instruction-trace port

Browse Source
This commit is contained in:
Andrew Waterman
2017-09-19 22:59:28 -07:00
parent acea94bcef
commit 4d6d6ff641
7 changed files with 62 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/IBuf.scala
View File

@@ -16,7 +16,6 @@ class Instruction(implicit val p: Parameters) extends ParameterizedBundle with H
val rvc = Bool()
val inst = new ExpandedInstruction
val raw = UInt(width = 32)
val cinst = UInt(width = 32)
require(coreInstBits == (if (usingCompressed) 16 else 32))
}
@@ -96,7 +95,6 @@ class IBuf(implicit p: Parameters) extends CoreModule {
exp.io.in := curInst
io.inst(i).bits.inst := exp.io.out
io.inst(i).bits.raw := curInst
io.inst(i).bits.cinst := Mux(exp.io.rvc, curInst & 0xFFFF, curInst)
if (usingCompressed) {
val replay = ic_replay(j) || (!exp.io.rvc && (btbHitMask(j) || ic_replay(j+1)))