riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

Browse Source 
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
This commit is contained in:
Henry Cook
2017-07-07 10:48:16 -07:00
committed by GitHub
parent c28c23150d
commit 4c595d175c
238 changed files with 1347 additions and 10978 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/util/AsyncQueue.scala
View File

@ -1,6 +1,7 @@
// See LICENSE.SiFive for license details.
package util
package freechips.rocketchip.util
import Chisel._
object GrayCounter {