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Refactor package hierarchy and remove legacy bus protocol implementations (#845)

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* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
This commit is contained in:
Henry Cook
2017-07-07 10:48:16 -07:00
committed by GitHub
parent c28c23150d
commit 4c595d175c
238 changed files with 1347 additions and 10978 deletions
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72
src/main/scala/unittest/Configs.scala
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@ -1,10 +1,15 @@
// See LICENSE.SiFive for license details.
package unittest
package freechips.rocketchip.unittest
import Chisel._
import config._
import rocketchip.{BaseConfig, BasePlatformConfig}
import freechips.rocketchip.amba.ahb._
import freechips.rocketchip.amba.apb._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.chip.{BaseConfig, BasePlatformConfig}
import freechips.rocketchip.config._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.tilelink._
case object TestDurationMultiplier extends Field[Int]
@ -12,22 +17,20 @@ class WithTestDuration(x: Int) extends Config((site, here, up) => {
case TestDurationMultiplier => x
})
class WithUncoreUnitTests extends Config((site, here, up) => {
case uncore.tilelink.TLId => "L1toL2"
class WithAMBAUnitTests extends Config((site, here, up) => {
case UnitTests => (q: Parameters) => {
implicit val p = q
val txns = 100 * site(TestDurationMultiplier)
val timeout = 50000 * site(TestDurationMultiplier)
Seq(
Module(new uncore.tilelink2.TLFuzzRAMTest( txns=3*txns, timeout=timeout)),
Module(new uncore.ahb.AHBBridgeTest(true, txns=8*txns, timeout=timeout)),
Module(new uncore.ahb.AHBNativeTest(true, txns=6*txns, timeout=timeout)),
Module(new uncore.ahb.AHBNativeTest(false, txns=6*txns, timeout=timeout)),
Module(new uncore.apb.APBBridgeTest(true, txns=6*txns, timeout=timeout)),
Module(new uncore.apb.APBBridgeTest(false, txns=6*txns, timeout=timeout)),
Module(new uncore.axi4.AXI4LiteFuzzRAMTest( txns=6*txns, timeout=timeout)),
Module(new uncore.axi4.AXI4FullFuzzRAMTest( txns=3*txns, timeout=timeout)),
Module(new uncore.axi4.AXI4BridgeTest( txns=3*txns, timeout=timeout))) }
Module(new AHBBridgeTest(true, txns=8*txns, timeout=timeout)),
Module(new AHBNativeTest(true, txns=6*txns, timeout=timeout)),
Module(new AHBNativeTest(false,txns=6*txns, timeout=timeout)),
Module(new APBBridgeTest(true, txns=6*txns, timeout=timeout)),
Module(new APBBridgeTest(false,txns=6*txns, timeout=timeout)),
Module(new AXI4LiteFuzzRAMTest(txns=6*txns, timeout=timeout)),
Module(new AXI4FullFuzzRAMTest(txns=3*txns, timeout=timeout)),
Module(new AXI4BridgeTest( txns=3*txns, timeout=timeout))) }
})
class WithTLSimpleUnitTests extends Config((site, here, up) => {
@ -36,15 +39,16 @@ class WithTLSimpleUnitTests extends Config((site, here, up) => {
val txns = 100 * site(TestDurationMultiplier)
val timeout = 50000 * site(TestDurationMultiplier)
Seq(
Module(new uncore.tilelink2.TLRAMSimpleTest(1, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMSimpleTest(4, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMSimpleTest(16, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMZeroDelayTest(4, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRR0Test( txns= 3*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRR1Test( txns= 3*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMRationalCrossingTest(txns= 3*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMAsyncCrossingTest( txns= 5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMAtomicAutomataTest( txns=10*txns, timeout=timeout)) ) }
Module(new TLRAMSimpleTest(1, txns=15*txns, timeout=timeout)),
Module(new TLRAMSimpleTest(4, txns=15*txns, timeout=timeout)),
Module(new TLRAMSimpleTest(16, txns=15*txns, timeout=timeout)),
Module(new TLRAMZeroDelayTest(4, txns=15*txns, timeout=timeout)),
Module(new TLFuzzRAMTest( txns= 3*txns, timeout=timeout)),
Module(new TLRR0Test( txns= 3*txns, timeout=timeout)),
Module(new TLRR1Test( txns= 3*txns, timeout=timeout)),
Module(new TLRAMRationalCrossingTest(txns= 3*txns, timeout=timeout)),
Module(new TLRAMAsyncCrossingTest( txns= 5*txns, timeout=timeout)),
Module(new TLRAMAtomicAutomataTest( txns=10*txns, timeout=timeout)) ) }
})
class WithTLWidthUnitTests extends Config((site, here, up) => {
@ -53,12 +57,12 @@ class WithTLWidthUnitTests extends Config((site, here, up) => {
val txns = 100 * site(TestDurationMultiplier)
val timeout = 50000 * site(TestDurationMultiplier)
Seq(
Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256, txns= 5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMFragmenterTest(16, 64, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 16, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1, 1, txns= 1*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64, txns= 4*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64, 4, txns= 5*txns, timeout=timeout)) ) }
Module(new TLRAMFragmenterTest( 4, 256, txns= 5*txns, timeout=timeout)),
Module(new TLRAMFragmenterTest(16, 64, txns=15*txns, timeout=timeout)),
Module(new TLRAMFragmenterTest( 4, 16, txns=15*txns, timeout=timeout)),
Module(new TLRAMWidthWidgetTest( 1, 1, txns= 1*txns, timeout=timeout)),
Module(new TLRAMWidthWidgetTest( 4, 64, txns= 4*txns, timeout=timeout)),
Module(new TLRAMWidthWidgetTest(64, 4, txns= 5*txns, timeout=timeout)) ) }
})
class WithTLXbarUnitTests extends Config((site, here, up) => {
@ -67,13 +71,13 @@ class WithTLXbarUnitTests extends Config((site, here, up) => {
val txns = 100 * site(TestDurationMultiplier)
val timeout = 50000 * site(TestDurationMultiplier)
Seq(
Module(new uncore.tilelink2.TLRAMXbarTest(1, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMXbarTest(2, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMXbarTest(8, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4, txns=2*txns, timeout=timeout)) ) }
Module(new TLRAMXbarTest(1, txns=5*txns, timeout=timeout)),
Module(new TLRAMXbarTest(2, txns=5*txns, timeout=timeout)),
Module(new TLRAMXbarTest(8, txns=5*txns, timeout=timeout)),
Module(new TLMulticlientXbarTest(4,4, txns=2*txns, timeout=timeout)) ) }
})
class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)
class AMBAUnitTestConfig extends Config(new WithAMBAUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)
class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)
class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)
class TLXbarUnitTestConfig extends Config(new WithTLXbarUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)

4
src/main/scala/unittest/Generator.scala
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@ -1,8 +1,8 @@
// See LICENSE.SiFive for license details.
package unittest
package freechips.rocketchip.unittest
object Generator extends util.GeneratorApp {
object Generator extends freechips.rocketchip.util.GeneratorApp {
val longName = names.topModuleProject + "." + names.configs
generateFirrtl
generateTestSuiteMakefrags // TODO: Needed only for legacy make targets

4
src/main/scala/unittest/TestHarness.scala
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@ -1,9 +1,9 @@
// See LICENSE.SiFive for license details.
package unittest
package freechips.rocketchip.unittest
import Chisel._
import config._
import freechips.rocketchip.config.Parameters
class TestHarness(implicit val p: Parameters) extends Module {
val io = new Bundle { val success = Bool(OUTPUT) }

6
src/main/scala/unittest/UnitTest.scala
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@ -1,10 +1,10 @@
// See LICENSE.SiFive for license details.
package unittest
package freechips.rocketchip.unittest
import Chisel._
import config._
import util.SimpleTimer
import freechips.rocketchip.config._
import freechips.rocketchip.util.SimpleTimer
trait HasUnitTestIO {
val io = new Bundle {