Refactor package hierarchy and remove legacy bus protocol implementations (#845)
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
This commit is contained in:
Henry Cook
GitHub
270
src/main/scala/tilelink/Xbar.scala
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270
src/main/scala/tilelink/Xbar.scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule
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{
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val node = TLNexusNode(
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numClientPorts = 1 to 32,
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numManagerPorts = 1 to 32,
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clientFn = { seq =>
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require (!seq.exists(_.unsafeAtomics) || seq.size == 1,
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"An unsafe atomic port can not be combined with any other!")
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seq(0).copy(
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minLatency = seq.map(_.minLatency).min,
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clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
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port.clients map { client => client.copy(
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sourceId = client.sourceId.shift(range.start)
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)}
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}
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)
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},
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managerFn = { seq =>
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val fifoIdFactory = TLXbar.relabeler()
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val outputIdRanges = TLXbar.mapOutputIds(seq)
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seq(0).copy(
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minLatency = seq.map(_.minLatency).min,
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endSinkId = outputIdRanges.map(_.map(_.end).getOrElse(0)).max,
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managers = seq.flatMap { port =>
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require (port.beatBytes == seq(0).beatBytes,
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s"Xbar data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
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val fifoIdMapper = fifoIdFactory()
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port.managers map { manager => manager.copy(
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fifoId = manager.fifoId.map(fifoIdMapper(_))
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)}
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}
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)
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})
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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// Grab the port ID mapping
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val inputIdRanges = TLXbar.mapInputIds(node.edgesIn.map(_.client))
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val outputIdRanges = TLXbar.mapOutputIds(node.edgesOut.map(_.manager))
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// Find a good mask for address decoding
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val port_addrs = node.edgesOut.map(_.manager.managers.map(_.address).flatten)
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val routingMask = AddressDecoder(port_addrs)
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val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
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val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
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// Print the address mapping
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if (false) {
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println("Xbar mapping:")
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route_addrs.foreach { p =>
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print(" ")
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p.foreach { a => print(s" ${a}") }
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println("")
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}
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println("--")
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}
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// Print the ID mapping
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if (false) {
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println(s"XBar ${name} mapping:")
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(node.edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
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println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
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}
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println("")
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}
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// We need an intermediate size of bundle with the widest possible identifiers
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val wide_bundle = TLBundleParameters.union(io.in.map(_.params) ++ io.out.map(_.params))
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// Handle size = 1 gracefully (Chisel3 empty range is broken)
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def trim(id: UInt, size: Int) = if (size <= 1) UInt(0) else id(log2Ceil(size)-1, 0)
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// Transform input bundle sources (sinks use global namespace on both sides)
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val in = Wire(Vec(io.in.size, TLBundle(wide_bundle)))
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for (i <- 0 until in.size) {
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val r = inputIdRanges(i)
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in(i).a <> io.in(i).a
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io.in(i).d <> in(i).d
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in(i).a.bits.source := io.in(i).a.bits.source | UInt(r.start)
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io.in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
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if (node.edgesIn(i).client.anySupportProbe && node.edgesOut.exists(_.manager.anySupportAcquireB)) {
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in(i).c <> io.in(i).c
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in(i).e <> io.in(i).e
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io.in(i).b <> in(i).b
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in(i).c.bits.source := io.in(i).c.bits.source | UInt(r.start)
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io.in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
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} else {
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in(i).c.valid := Bool(false)
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in(i).e.valid := Bool(false)
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in(i).b.ready := Bool(false)
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io.in(i).c.ready := Bool(true)
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io.in(i).e.ready := Bool(true)
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io.in(i).b.valid := Bool(false)
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}
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}
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// Transform output bundle sinks (sources use global namespace on both sides)
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val out = Wire(Vec(io.out.size, TLBundle(wide_bundle)))
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for (i <- 0 until out.size) {
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val r = outputIdRanges(i)
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io.out(i).a <> out(i).a
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out(i).d <> io.out(i).d
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out(i).d.bits.sink := io.out(i).d.bits.sink | UInt(r.map(_.start).getOrElse(0))
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if (node.edgesOut(i).manager.anySupportAcquireB && node.edgesIn.exists(_.client.anySupportProbe)) {
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io.out(i).c <> out(i).c
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io.out(i).e <> out(i).e
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out(i).b <> io.out(i).b
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io.out(i).e.bits.sink := trim(out(i).e.bits.sink, r.map(_.size).getOrElse(0))
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} else {
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out(i).c.ready := Bool(false)
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out(i).e.ready := Bool(false)
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out(i).b.valid := Bool(false)
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io.out(i).c.valid := Bool(false)
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io.out(i).e.valid := Bool(false)
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io.out(i).b.ready := Bool(true)
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}
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}
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val addressA = (in zip node.edgesIn) map { case (i, e) => e.address(i.a.bits) }
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val addressC = (in zip node.edgesIn) map { case (i, e) => e.address(i.c.bits) }
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val requestAIO = Vec(addressA.map { i => Vec(outputPorts.map { o => o(i) }) })
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val requestCIO = Vec(addressC.map { i => Vec(outputPorts.map { o => o(i) }) })
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val requestBOI = Vec(out.map { o => Vec(inputIdRanges.map { i => i.contains(o.b.bits.source) }) })
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val requestDOI = Vec(out.map { o => Vec(inputIdRanges.map { i => i.contains(o.d.bits.source) }) })
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val requestEIO = Vec(in.map { i => Vec(outputIdRanges.map { o => o.map(_.contains(i.e.bits.sink)).getOrElse(Bool(false)) }) })
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val beatsAI = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) })
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val beatsBO = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) })
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val beatsCI = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) })
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val beatsDO = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) })
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val beatsEI = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) })
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// Which pairs support support transfers
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def transpose[T](x: Seq[Seq[T]]) = Seq.tabulate(x(0).size) { i => Seq.tabulate(x.size) { j => x(j)(i) } }
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def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
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// Fanout the input sources to the output sinks
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val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r) })
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val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r) })
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val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r) })
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val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r) })
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val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r) })
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// Arbitrate amongst the sources
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for (o <- 0 until out.size) {
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val allowI = Seq.tabulate(in.size) { i =>
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node.edgesIn(i).client.anySupportProbe &&
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node.edgesOut(o).manager.anySupportAcquireB
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}
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TLArbiter(policy)(out(o).a, (beatsAI zip portsAOI(o) ):_*)
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TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), allowI):_*)
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TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), allowI):_*)
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}
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for (i <- 0 until in.size) {
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val allowO = Seq.tabulate(out.size) { o =>
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node.edgesIn(i).client.anySupportProbe &&
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node.edgesOut(o).manager.anySupportAcquireB
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}
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TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), allowO):_*)
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TLArbiter(policy)(in(i).d, (beatsDO zip portsDIO(i) ):_*)
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}
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}
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}
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object TLXbar
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{
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def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId)).map(_.get)
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def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
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def assignRanges(sizes: Seq[Int]) = {
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val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
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val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
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val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
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val ranges = (tuples zip starts) map { case ((sz, i), st) =>
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(if (sz == 0) None else Some(IdRange(st, st+sz)), i)
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}
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ranges.sortBy(_._2).map(_._1) // Restore orignal order
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}
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def relabeler() = {
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var idFactory = 0
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() => {
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val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
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(x: Int) => {
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if (fifoMap.contains(x)) fifoMap(x) else {
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val out = idFactory
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idFactory = idFactory + 1
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fifoMap += (x -> out)
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out
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}
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}
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}
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}
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// Replicate an input port to each output port
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def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool]) = {
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val filtered = Wire(Vec(select.size, input))
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for (i <- 0 until select.size) {
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filtered(i).bits := input.bits
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filtered(i).valid := input.valid && select(i)
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}
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input.ready := Mux1H(select, filtered.map(_.ready))
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filtered
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}
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}
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/** Synthesizeable unit tests */
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import freechips.rocketchip.unittest._
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class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
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val fuzz = LazyModule(new TLFuzzer(txns))
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val model = LazyModule(new TLRAMModel("Xbar"))
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val xbar = LazyModule(new TLXbar)
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(model.node)
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(0 until nManagers) foreach { n =>
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val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
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ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
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}
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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}
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}
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class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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io.finished := Module(LazyModule(new TLRAMXbar(nManagers,txns)).module).io.finished
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}
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class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
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val xbar = LazyModule(new TLXbar)
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val fuzzers = (0 until nClients) map { n =>
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val fuzz = LazyModule(new TLFuzzer(txns))
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xbar.node := TLDelayer(0.1)(fuzz.node)
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fuzz
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}
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(0 until nManagers) foreach { n =>
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val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
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ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
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}
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzzers.last.module.io.finished
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}
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}
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class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module).io.finished
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}
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