Refactor package hierarchy and remove legacy bus protocol implementations (#845)
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
This commit is contained in:
Henry Cook
GitHub
395
src/main/scala/tilelink/Parameters.scala
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395
src/main/scala/tilelink/Parameters.scala
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@ -0,0 +1,395 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.RationalDirection
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import scala.math.max
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case class TLManagerParameters(
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address: Seq[AddressSet],
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resources: Seq[Resource] = Seq(),
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regionType: RegionType.T = RegionType.GET_EFFECTS,
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executable: Boolean = false, // processor can execute from this memory
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nodePath: Seq[BaseNode] = Seq(),
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// Supports both Acquire+Release+Finish of these sizes
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supportsAcquireT: TransferSizes = TransferSizes.none,
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supportsAcquireB: TransferSizes = TransferSizes.none,
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supportsArithmetic: TransferSizes = TransferSizes.none,
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supportsLogical: TransferSizes = TransferSizes.none,
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supportsGet: TransferSizes = TransferSizes.none,
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supportsPutFull: TransferSizes = TransferSizes.none,
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supportsPutPartial: TransferSizes = TransferSizes.none,
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supportsHint: TransferSizes = TransferSizes.none,
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// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
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// Note: you can only rely on this FIFO behaviour if your TLClientParameters include requestFifo
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fifoId: Option[Int] = None)
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{
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require (!address.isEmpty)
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address.foreach { a => require (a.finite) }
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address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
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require (supportsPutFull.contains(supportsPutPartial))
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require (supportsPutFull.contains(supportsArithmetic))
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require (supportsPutFull.contains(supportsLogical))
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require (supportsGet.contains(supportsArithmetic))
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require (supportsGet.contains(supportsLogical))
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require (supportsAcquireB.contains(supportsAcquireT))
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// Make sure that the regionType agrees with the capabilities
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require ((regionType == RegionType.CACHED || regionType == RegionType.TRACKED) != supportsAcquireB.none)
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require (regionType != RegionType.UNCACHED || supportsGet)
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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val maxTransfer = List( // Largest supported transfer of all types
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supportsAcquireT.max,
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supportsAcquireB.max,
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supportsArithmetic.max,
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supportsLogical.max,
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supportsGet.max,
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supportsPutFull.max,
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supportsPutPartial.max).max
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val maxAddress = address.map(_.max).max
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val minAlignment = address.map(_.alignment).min
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// The device had better not support a transfer larger than its alignment
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require (minAlignment >= maxTransfer, s"minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
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def toResource: ResourceAddress = {
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ResourceAddress(address, ResourcePermissions(
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r = supportsAcquireB || supportsGet,
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w = supportsAcquireT || supportsPutFull,
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x = executable,
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c = supportsAcquireB))
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}
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}
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case class TLManagerPortParameters(
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managers: Seq[TLManagerParameters],
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beatBytes: Int,
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endSinkId: Int = 0, // 0 = no sink ids, 1 = a reusable sink id, >1 = unique sink ids
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minLatency: Int = 0)
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{
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require (!managers.isEmpty)
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require (isPow2(beatBytes))
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require (endSinkId >= 0)
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require (minLatency >= 0)
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def requireFifo() = managers.foreach { m =>require (m.fifoId == Some(0)) }
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// Bounds on required sizes
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def maxAddress = managers.map(_.maxAddress).max
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def maxTransfer = managers.map(_.maxTransfer).max
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// Operation sizes supported by all outward Managers
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val allSupportAcquireT = managers.map(_.supportsAcquireT) .reduce(_ intersect _)
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val allSupportAcquireB = managers.map(_.supportsAcquireB) .reduce(_ intersect _)
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val allSupportArithmetic = managers.map(_.supportsArithmetic).reduce(_ intersect _)
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val allSupportLogical = managers.map(_.supportsLogical) .reduce(_ intersect _)
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val allSupportGet = managers.map(_.supportsGet) .reduce(_ intersect _)
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val allSupportPutFull = managers.map(_.supportsPutFull) .reduce(_ intersect _)
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val allSupportPutPartial = managers.map(_.supportsPutPartial).reduce(_ intersect _)
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val allSupportHint = managers.map(_.supportsHint) .reduce(_ intersect _)
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// Operation supported by at least one outward Managers
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val anySupportAcquireT = managers.map(!_.supportsAcquireT.none) .reduce(_ || _)
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val anySupportAcquireB = managers.map(!_.supportsAcquireB.none) .reduce(_ || _)
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val anySupportArithmetic = managers.map(!_.supportsArithmetic.none).reduce(_ || _)
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val anySupportLogical = managers.map(!_.supportsLogical.none) .reduce(_ || _)
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val anySupportGet = managers.map(!_.supportsGet.none) .reduce(_ || _)
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val anySupportPutFull = managers.map(!_.supportsPutFull.none) .reduce(_ || _)
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val anySupportPutPartial = managers.map(!_.supportsPutPartial.none).reduce(_ || _)
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val anySupportHint = managers.map(!_.supportsHint.none) .reduce(_ || _)
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// These return Option[TLManagerParameters] for your convenience
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def find(address: BigInt) = managers.find(_.address.exists(_.contains(address)))
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// The safe version will check the entire address
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def findSafe(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
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// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
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def findFast(address: UInt) = {
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val routingMask = AddressDecoder(managers.map(_.address))
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Vec(managers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
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}
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// Compute the simplest AddressSets that decide a key
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def fastPropertyGroup[K](p: TLManagerParameters => K): Map[K, Seq[AddressSet]] = {
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val groups = managers.map(m => (p(m), m.address)).groupBy(_._1).mapValues(_.flatMap(_._2))
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val reductionMask = AddressDecoder(groups.values.toList)
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groups.mapValues(seq => AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct))
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}
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// Select a property
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def fastProperty[K, D <: Data](address: UInt, p: TLManagerParameters => K, d: K => D): D =
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Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
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// Note: returns the actual fifoId + 1 or 0 if None
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def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => UInt(i))
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def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => Bool(b))
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// Does this Port manage this ID/address?
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def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
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private def supportHelper(
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safe: Boolean,
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member: TLManagerParameters => TransferSizes,
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address: UInt,
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lgSize: UInt,
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range: Option[TransferSizes]): Bool = {
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def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
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val supportCases = managers.groupBy(m => trim(member(m))).mapValues(_.flatMap(_.address))
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val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.values.toList)
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val simplified = supportCases.mapValues(seq => AddressSet.unify(seq.map(_.widen(~mask)).distinct))
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simplified.map { case (s, a) =>
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(Bool(Some(s) == range) || s.containsLg(lgSize)) &&
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a.map(_.contains(address)).reduce(_||_)
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}.foldLeft(Bool(false))(_||_)
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}
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// Check for support of a given operation at a specific address
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def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsAcquireT, address, lgSize, range)
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def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsAcquireB, address, lgSize, range)
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def supportsArithmeticSafe(address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsArithmetic, address, lgSize, range)
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def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsLogical, address, lgSize, range)
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def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsGet, address, lgSize, range)
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def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsPutFull, address, lgSize, range)
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def supportsPutPartialSafe(address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsPutPartial, address, lgSize, range)
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def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsHint, address, lgSize, range)
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def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsAcquireT, address, lgSize, range)
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def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsAcquireB, address, lgSize, range)
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def supportsArithmeticFast(address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsArithmetic, address, lgSize, range)
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def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsLogical, address, lgSize, range)
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def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsGet, address, lgSize, range)
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def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsPutFull, address, lgSize, range)
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def supportsPutPartialFast(address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsPutPartial, address, lgSize, range)
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def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsHint, address, lgSize, range)
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}
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case class TLClientParameters(
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name: String,
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sourceId: IdRange = IdRange(0,1),
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nodePath: Seq[BaseNode] = Seq(),
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requestFifo: Boolean = false, // only a request, not a requirement
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// Supports both Probe+Grant of these sizes
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supportsProbe: TransferSizes = TransferSizes.none,
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supportsArithmetic: TransferSizes = TransferSizes.none,
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supportsLogical: TransferSizes = TransferSizes.none,
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supportsGet: TransferSizes = TransferSizes.none,
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supportsPutFull: TransferSizes = TransferSizes.none,
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supportsPutPartial: TransferSizes = TransferSizes.none,
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supportsHint: TransferSizes = TransferSizes.none)
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{
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require (supportsPutFull.contains(supportsPutPartial))
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// We only support these operations if we support Probe (ie: we're a cache)
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require (supportsProbe.contains(supportsArithmetic))
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require (supportsProbe.contains(supportsLogical))
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require (supportsProbe.contains(supportsGet))
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require (supportsProbe.contains(supportsPutFull))
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require (supportsProbe.contains(supportsPutPartial))
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require (supportsProbe.contains(supportsHint))
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// If you need FIFO, you better not be TL-C (due to independent A vs. C order)
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require (!requestFifo || !supportsProbe)
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val maxTransfer = List(
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supportsProbe.max,
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supportsArithmetic.max,
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supportsLogical.max,
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supportsGet.max,
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supportsPutFull.max,
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supportsPutPartial.max).max
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}
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case class TLClientPortParameters(
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clients: Seq[TLClientParameters],
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unsafeAtomics: Boolean = false,
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minLatency: Int = 0) // Only applies to B=>C
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{
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require (!clients.isEmpty)
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require (minLatency >= 0)
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// Require disjoint ranges for Ids
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IdRange.overlaps(clients.map(_.sourceId)).foreach { case (x, y) =>
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require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
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}
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// Bounds on required sizes
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def endSourceId = clients.map(_.sourceId.end).max
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def maxTransfer = clients.map(_.maxTransfer).max
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// Operation sizes supported by all inward Clients
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val allSupportProbe = clients.map(_.supportsProbe) .reduce(_ intersect _)
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val allSupportArithmetic = clients.map(_.supportsArithmetic).reduce(_ intersect _)
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val allSupportLogical = clients.map(_.supportsLogical) .reduce(_ intersect _)
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val allSupportGet = clients.map(_.supportsGet) .reduce(_ intersect _)
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val allSupportPutFull = clients.map(_.supportsPutFull) .reduce(_ intersect _)
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val allSupportPutPartial = clients.map(_.supportsPutPartial).reduce(_ intersect _)
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val allSupportHint = clients.map(_.supportsHint) .reduce(_ intersect _)
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// Operation is supported by at least one client
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val anySupportProbe = clients.map(!_.supportsProbe.none) .reduce(_ || _)
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val anySupportArithmetic = clients.map(!_.supportsArithmetic.none).reduce(_ || _)
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val anySupportLogical = clients.map(!_.supportsLogical.none) .reduce(_ || _)
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val anySupportGet = clients.map(!_.supportsGet.none) .reduce(_ || _)
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val anySupportPutFull = clients.map(!_.supportsPutFull.none) .reduce(_ || _)
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val anySupportPutPartial = clients.map(!_.supportsPutPartial.none).reduce(_ || _)
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val anySupportHint = clients.map(!_.supportsHint.none) .reduce(_ || _)
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// These return Option[TLClientParameters] for your convenience
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def find(id: Int) = clients.find(_.sourceId.contains(id))
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// Synthesizable lookup methods
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def find(id: UInt) = Vec(clients.map(_.sourceId.contains(id)))
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def contains(id: UInt) = find(id).reduce(_ || _)
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def requestFifo(id: UInt) = Mux1H(find(id), clients.map(c => Bool(c.requestFifo)))
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private def safety_helper(member: TLClientParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
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val allSame = clients.map(member(_) == member(clients(0))).reduce(_ && _)
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if (allSame) member(clients(0)).containsLg(lgSize) else {
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Mux1H(find(id), clients.map(member(_).containsLg(lgSize)))
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}
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}
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// Check for support of a given operation at a specific id
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val supportsProbe = safety_helper(_.supportsProbe) _
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val supportsArithmetic = safety_helper(_.supportsArithmetic) _
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val supportsLogical = safety_helper(_.supportsLogical) _
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val supportsGet = safety_helper(_.supportsGet) _
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val supportsPutFull = safety_helper(_.supportsPutFull) _
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val supportsPutPartial = safety_helper(_.supportsPutPartial) _
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val supportsHint = safety_helper(_.supportsHint) _
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}
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case class TLBundleParameters(
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addressBits: Int,
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dataBits: Int,
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sourceBits: Int,
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sinkBits: Int,
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sizeBits: Int)
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{
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// Chisel has issues with 0-width wires
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require (addressBits >= 1)
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require (dataBits >= 8)
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require (sourceBits >= 1)
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require (sinkBits >= 1)
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require (sizeBits >= 1)
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require (isPow2(dataBits))
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val addrLoBits = log2Up(dataBits/8)
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def union(x: TLBundleParameters) =
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TLBundleParameters(
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max(addressBits, x.addressBits),
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max(dataBits, x.dataBits),
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max(sourceBits, x.sourceBits),
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max(sinkBits, x.sinkBits),
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max(sizeBits, x.sizeBits))
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}
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object TLBundleParameters
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{
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val emptyBundleParams = TLBundleParameters(
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addressBits = 1,
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dataBits = 8,
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sourceBits = 1,
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sinkBits = 1,
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sizeBits = 1)
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def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
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def apply(client: TLClientPortParameters, manager: TLManagerPortParameters) =
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new TLBundleParameters(
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addressBits = log2Up(manager.maxAddress + 1),
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dataBits = manager.beatBytes * 8,
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sourceBits = log2Up(client.endSourceId),
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sinkBits = log2Up(manager.endSinkId),
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sizeBits = log2Up(log2Ceil(max(client.maxTransfer, manager.maxTransfer))+1))
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}
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case class TLEdgeParameters(
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client: TLClientPortParameters,
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manager: TLManagerPortParameters)
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{
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val maxTransfer = max(client.maxTransfer, manager.maxTransfer)
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val maxLgSize = log2Ceil(maxTransfer)
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// Sanity check the link...
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require (maxTransfer >= manager.beatBytes)
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val bundle = TLBundleParameters(client, manager)
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}
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case class TLAsyncManagerPortParameters(depth: Int, base: TLManagerPortParameters) { require (isPow2(depth)) }
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case class TLAsyncClientPortParameters(base: TLClientPortParameters)
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case class TLAsyncBundleParameters(depth: Int, base: TLBundleParameters)
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{
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require (isPow2(depth))
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def union(x: TLAsyncBundleParameters) = TLAsyncBundleParameters(
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depth = max(depth, x.depth),
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base = base.union(x.base))
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}
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object TLAsyncBundleParameters
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{
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val emptyBundleParams = TLAsyncBundleParameters(depth = 1, base = TLBundleParameters.emptyBundleParams)
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def union(x: Seq[TLAsyncBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
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}
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case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters)
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{
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val bundle = TLAsyncBundleParameters(manager.depth, TLBundleParameters(client.base, manager.base))
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}
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case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLManagerPortParameters)
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case class TLRationalClientPortParameters(base: TLClientPortParameters)
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case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters)
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{
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val bundle = TLBundleParameters(client.base, manager.base)
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}
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object ManagerUnification
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{
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def apply(managers: Seq[TLManagerParameters]) = {
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// To be unified, devices must agree on all of these terms
|
||||
case class TLManagerKey(
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resources: Seq[Resource],
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regionType: RegionType.T,
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||||
executable: Boolean,
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||||
supportsAcquireT: TransferSizes,
|
||||
supportsAcquireB: TransferSizes,
|
||||
supportsArithmetic: TransferSizes,
|
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supportsLogical: TransferSizes,
|
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supportsGet: TransferSizes,
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supportsPutFull: TransferSizes,
|
||||
supportsPutPartial: TransferSizes,
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supportsHint: TransferSizes)
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def key(x: TLManagerParameters) = TLManagerKey(
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resources = x.resources,
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regionType = x.regionType,
|
||||
executable = x.executable,
|
||||
supportsAcquireT = x.supportsAcquireT,
|
||||
supportsAcquireB = x.supportsAcquireB,
|
||||
supportsArithmetic = x.supportsArithmetic,
|
||||
supportsLogical = x.supportsLogical,
|
||||
supportsGet = x.supportsGet,
|
||||
supportsPutFull = x.supportsPutFull,
|
||||
supportsPutPartial = x.supportsPutPartial,
|
||||
supportsHint = x.supportsHint)
|
||||
val map = scala.collection.mutable.HashMap[TLManagerKey, TLManagerParameters]()
|
||||
managers.foreach { m =>
|
||||
val k = key(m)
|
||||
map.get(k) match {
|
||||
case None => map.update(k, m)
|
||||
case Some(n) => {
|
||||
map.update(k, m.copy(
|
||||
address = m.address ++ n.address,
|
||||
fifoId = None)) // Merging means it's not FIFO anymore!
|
||||
}
|
||||
}
|
||||
}
|
||||
map.values.map(m => m.copy(address = AddressSet.unify(m.address))).toList
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user