Refactor package hierarchy and remove legacy bus protocol implementations (#845)
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
This commit is contained in:
Henry Cook
GitHub
201
src/main/scala/tilelink/Nodes.scala
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201
src/main/scala/tilelink/Nodes.scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.RationalDirection
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import scala.collection.mutable.ListBuffer
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case object TLMonitorBuilder extends Field[TLMonitorArgs => Option[TLMonitorBase]]
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case object TLCombinationalCheck extends Field[Boolean]
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object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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{
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def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu)
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def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(pd, pu)
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def bundleO(eo: TLEdgeOut): TLBundle = TLBundle(eo.bundle)
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def bundleI(ei: TLEdgeIn): TLBundle = TLBundle(ei.bundle)
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def colour = "#000000" // black
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override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString
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override def labelO(eo: TLEdgeOut) = (eo.manager.beatBytes * 8).toString
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override def connect(edges: () => Seq[TLEdgeIn], bundles: () => Seq[(TLBundle, TLBundle)], enableMonitoring: Boolean)
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(implicit p: Parameters, sourceInfo: SourceInfo): (Option[TLMonitorBase], () => Unit) = {
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val monitor = if (enableMonitoring) p(TLMonitorBuilder)(TLMonitorArgs(edges, sourceInfo, p)) else None
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(monitor, () => {
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val eval = bundles ()
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monitor.foreach { m => (eval zip m.module.io.in) foreach { case ((i,o), m) => m := TLBundleSnoop(o,i) } }
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eval.foreach { case (bi, bo) =>
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bi <> bo
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if (p(TLCombinationalCheck)) {
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// It is forbidden for valid to depend on ready in TL2
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// If someone did that, then this will create a detectable combinational loop
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bo.a.ready := bi.a.ready && bo.a.valid
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bi.b.ready := bo.b.ready && bi.b.valid
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bo.c.ready := bi.c.ready && bo.c.valid
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bi.d.ready := bo.d.ready && bi.d.valid
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bo.e.ready := bi.e.ready && bo.e.valid
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}
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}
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})
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}
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override def mixO(pd: TLClientPortParameters, node: OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLClientPortParameters =
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pd.copy(clients = pd.clients.map { c => c.copy (nodePath = node +: c.nodePath) })
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override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLManagerPortParameters =
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pu.copy(managers = pu.managers.map { m => m.copy (nodePath = node +: m.nodePath) })
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override def getO(pu: TLManagerPortParameters): Option[BaseNode] = {
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val head = pu.managers.map(_.nodePath.headOption)
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if (head.exists(!_.isDefined) || head.map(_.get).distinct.size != 1) {
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None
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} else {
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val subproblem = pu.copy(managers = pu.managers.map(m => m.copy(nodePath = m.nodePath.tail)))
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getO(subproblem) match {
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case Some(x) => Some(x)
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case None => Some(head(0).get)
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}
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}
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}
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}
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// Nodes implemented inside modules
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case class TLIdentityNode() extends IdentityNode(TLImp)
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case class TLClientNode(portParams: Seq[TLClientPortParameters]) extends SourceNode(TLImp)(portParams)
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case class TLManagerNode(portParams: Seq[TLManagerPortParameters]) extends SinkNode(TLImp)(portParams)
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object TLClientNode
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{
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def apply(params: TLClientParameters) =
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new TLClientNode(Seq(TLClientPortParameters(Seq(params))))
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}
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object TLManagerNode
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{
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def apply(beatBytes: Int, params: TLManagerParameters) =
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new TLManagerNode(Seq(TLManagerPortParameters(Seq(params), beatBytes, minLatency = 0)))
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}
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case class TLAdapterNode(
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clientFn: TLClientPortParameters => TLClientPortParameters,
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managerFn: TLManagerPortParameters => TLManagerPortParameters,
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num: Range.Inclusive = 0 to 999)
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extends AdapterNode(TLImp)(clientFn, managerFn, num)
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case class TLNexusNode(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 999,
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numManagerPorts: Range.Inclusive = 1 to 999)
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extends NexusNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
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case class TLSplitterNode(
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clientFn: SplitterArg[TLClientPortParameters] => Seq[TLClientPortParameters],
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managerFn: SplitterArg[TLManagerPortParameters] => Seq[TLManagerPortParameters],
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numClientPorts: Range.Inclusive = 0 to 999,
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numManagerPorts: Range.Inclusive = 0 to 999)
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extends SplitterNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
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abstract class TLCustomNode(
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numClientPorts: Range.Inclusive,
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numManagerPorts: Range.Inclusive)
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extends CustomNode(TLImp)(numClientPorts, numManagerPorts)
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// Nodes passed from an inner module
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case class TLOutputNode() extends OutputNode(TLImp)
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case class TLInputNode() extends InputNode(TLImp)
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// Nodes used for external ports
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case class TLBlindOutputNode(portParams: Seq[TLManagerPortParameters]) extends BlindOutputNode(TLImp)(portParams)
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case class TLBlindInputNode(portParams: Seq[TLClientPortParameters]) extends BlindInputNode(TLImp)(portParams)
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case class TLInternalOutputNode(portParams: Seq[TLManagerPortParameters]) extends InternalOutputNode(TLImp)(portParams)
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case class TLInternalInputNode(portParams: Seq[TLClientPortParameters]) extends InternalInputNode(TLImp)(portParams)
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/** Synthesizeable unit tests */
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import freechips.rocketchip.unittest._
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class TLInputNodeTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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class Acceptor extends LazyModule {
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val node = TLInputNode()
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val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff)))
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tlram.node := node
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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}
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}
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val fuzzer = LazyModule(new TLFuzzer(txns))
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LazyModule(new Acceptor).node := TLFragmenter(4, 64)(fuzzer.node)
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io.finished := Module(fuzzer.module).io.finished
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}
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object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncEdgeParameters, TLAsyncBundle]
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{
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def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
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def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
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def bundleO(eo: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(eo.bundle)
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def bundleI(ei: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(ei.bundle)
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def colour = "#ff0000" // red
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override def labelI(ei: TLAsyncEdgeParameters) = ei.manager.depth.toString
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override def labelO(eo: TLAsyncEdgeParameters) = eo.manager.depth.toString
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override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
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pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) }))
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override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
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pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
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}
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case class TLAsyncIdentityNode() extends IdentityNode(TLAsyncImp)
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case class TLAsyncOutputNode() extends OutputNode(TLAsyncImp)
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case class TLAsyncInputNode() extends InputNode(TLAsyncImp)
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case class TLAsyncSourceNode(sync: Int)
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extends MixedAdapterNode(TLImp, TLAsyncImp)(
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dFn = { p => TLAsyncClientPortParameters(p) },
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uFn = { p => p.base.copy(minLatency = sync+1) }) // discard cycles in other clock domain
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case class TLAsyncSinkNode(depth: Int, sync: Int)
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extends MixedAdapterNode(TLAsyncImp, TLImp)(
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dFn = { p => p.base.copy(minLatency = sync+1) },
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uFn = { p => TLAsyncManagerPortParameters(depth, p) })
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object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalEdgeParameters, TLRationalBundle]
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{
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def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu)
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def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu)
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def bundleO(eo: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(eo.bundle)
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def bundleI(ei: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(ei.bundle)
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def colour = "#00ff00" // green
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override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
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pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) }))
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override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
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pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
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}
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case class TLRationalIdentityNode() extends IdentityNode(TLRationalImp)
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case class TLRationalOutputNode() extends OutputNode(TLRationalImp)
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case class TLRationalInputNode() extends InputNode(TLRationalImp)
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case class TLRationalSourceNode()
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extends MixedAdapterNode(TLImp, TLRationalImp)(
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dFn = { p => TLRationalClientPortParameters(p) },
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uFn = { p => p.base.copy(minLatency = 1) }) // discard cycles from other clock domain
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case class TLRationalSinkNode(direction: RationalDirection)
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extends MixedAdapterNode(TLRationalImp, TLImp)(
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dFn = { p => p.base.copy(minLatency = 1) },
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uFn = { p => TLRationalManagerPortParameters(direction, p) })
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