Refactor package hierarchy and remove legacy bus protocol implementations (#845)

* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package

src/main/scala/tilelink/Example.scala

@@ -0,0 +1,40 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.tilelink
+
+import Chisel._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+
+case class ExampleParams(num: Int, address: BigInt)
+
+trait ExampleBundle
+{
+  val params: ExampleParams
+  val gpio = UInt(width = params.num)
+}
+
+trait ExampleModule extends HasRegMap
+{
+  val params: ExampleParams
+  val io: ExampleBundle
+  val interrupts: Vec[Bool]
+
+  val state = RegInit(UInt(0))
+  val pending = RegInit(UInt(0xf, width = 4))
+
+  io.gpio := state
+  interrupts := pending.toBools
+
+  regmap(
+    0 -> Seq(
+      RegField(params.num, state)),
+    4 -> Seq(
+      RegField.w1ToClear(4, pending, state)))
+}
+
+// Create a concrete TL2 version of the abstract Example slave
+class TLExample(params: ExampleParams)(implicit p: Parameters)
+  extends TLRegisterRouter(params.address, "somedev", Seq("ucbbar,random-interface"), 4)(
+  new TLRegBundle(params, _)    with ExampleBundle)(
+  new TLRegModule(params, _, _) with ExampleModule)