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Refactor package hierarchy and remove legacy bus protocol implementations (#845)

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* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
This commit is contained in:
Henry Cook
2017-07-07 10:48:16 -07:00
committed by GitHub
parent c28c23150d
commit 4c595d175c
238 changed files with 1347 additions and 10978 deletions
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14
src/main/scala/tile/FPU.scala
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@ -1,16 +1,15 @@
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package tile
package freechips.rocketchip.tile
import Chisel._
import Chisel.ImplicitConversions._
import FPConstants._
import rocket.DecodeLogic
import rocket.Instructions._
import uncore.constants.MemoryOpConstants._
import config._
import util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
case class FPUParams(
divSqrt: Boolean = true,
@ -23,6 +22,7 @@ object FPConstants
val RM_SZ = 3
val FLAGS_SZ = 5
}
import FPConstants._
trait HasFPUCtrlSigs {
val ldst = Bool()