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Refactor package hierarchy and remove legacy bus protocol implementations (#845)

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* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
This commit is contained in:
Henry Cook
2017-07-07 10:48:16 -07:00
committed by GitHub
parent c28c23150d
commit 4c595d175c
238 changed files with 1347 additions and 10978 deletions
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20
src/main/scala/tile/BaseTile.scala
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@ -1,13 +1,14 @@
// See LICENSE.SiFive for license details.
package tile
package freechips.rocketchip.tile
import Chisel._
import config._
import diplomacy._
import rocket._
import uncore.tilelink2._
import util._
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
case object SharedMemoryTLEdge extends Field[TLEdgeOut]
case object TileKey extends Field[TileParams]
@ -78,17 +79,14 @@ trait HasExternallyDrivenTileConstants extends Bundle {
/** Base class for all Tiles that use TileLink */
abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
with HasTileLinkMasterPort
with HasExternalInterrupts {
with HasTileParameters
with HasTileLinkMasterPort {
override lazy val module = new BaseTileModule(this, () => new BaseTileBundle(this))
}
class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
with HasTileParameters
with HasTileLinkMasterPortBundle
with HasExternalInterruptsBundle
with HasExternallyDrivenTileConstants
class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
with HasTileLinkMasterPortModule
with HasExternalInterruptsModule

9
src/main/scala/tile/Core.scala
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@ -1,11 +1,12 @@
// See LICENSE.SiFive for license details.
package tile
package freechips.rocketchip.tile
import Chisel._
import config._
import rocket._
import util._
import freechips.rocketchip.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
case object BuildCore extends Field[Parameters => CoreModule with HasCoreIO]
case object XLen extends Field[Int]

14
src/main/scala/tile/FPU.scala
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@ -1,16 +1,15 @@
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package tile
package freechips.rocketchip.tile
import Chisel._
import Chisel.ImplicitConversions._
import FPConstants._
import rocket.DecodeLogic
import rocket.Instructions._
import uncore.constants.MemoryOpConstants._
import config._
import util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
case class FPUParams(
divSqrt: Boolean = true,
@ -23,6 +22,7 @@ object FPConstants
val RM_SZ = 3
val FLAGS_SZ = 5
}
import FPConstants._
trait HasFPUCtrlSigs {
val ldst = Bool()

9
src/main/scala/tile/Interrupts.scala
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@ -1,11 +1,12 @@
// See LICENSE.SiFive for license details.
package tile
package freechips.rocketchip.tile
import Chisel._
import config.Parameters
import uncore.tilelink2.{IntSinkNode, IntSinkPortSimple}
import util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.tilelink.{IntSinkNode, IntSinkPortSimple}
import freechips.rocketchip.util._
class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
val debug = Bool()

14
src/main/scala/tile/L1Cache.scala
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@ -1,14 +1,14 @@
// See LICENSE.SiFive for license details.
package tile
package freechips.rocketchip.tile
import Chisel._
import config.{Parameters, Field}
import coreplex.CacheBlockBytes
import rocket.PAddrBits
import uncore.tilelink2.ClientMetadata
import uncore.util.{Code, IdentityCode}
import util.ParameterizedBundle
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.rocket.PAddrBits
import freechips.rocketchip.tilelink.ClientMetadata
import freechips.rocketchip.util._
trait L1CacheParams {
def nSets: Int

16
src/main/scala/tile/LazyRoCC.scala
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@ -1,14 +1,16 @@
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package tile
package freechips.rocketchip.tile
import Chisel._
import config._
import coreplex._
import diplomacy._
import rocket._
import uncore.tilelink2._
import freechips.rocketchip.config._
import freechips.rocketchip.coreplex._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.InOrderArbiter
case object RoccNPTWPorts extends Field[Int]
case object BuildRoCC extends Field[Seq[RoCCParams]]
@ -206,7 +208,7 @@ class AccumulatorExampleModule(outer: AccumulatorExample, n: Int = 4)(implicit p
io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp
io.mem.req.bits.addr := addend
io.mem.req.bits.tag := addr
io.mem.req.bits.cmd := uncore.constants.M_XRD // perform a load (M_XWR for stores)
io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
io.mem.req.bits.data := Bits(0) // we're not performing any stores...
io.mem.req.bits.phys := Bool(false)

3
src/main/scala/tile/Package.scala
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@ -1,3 +0,0 @@
// See LICENSE.SiFive for license details.
package object tile extends rocket.constants.ScalarOpConstants