riscv/rocket-chip
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)

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* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
This commit is contained in:
Henry Cook authored and GitHub committed 2017-07-07 10:48:16 -07:00
1 parent c28c23150d
commit 4c595d175c
238 files changed
+1347 -10978
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src/main/scala/rocket/NBDcache.scala
+5 -7
View File
@@ -1,16 +1,14 @@
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package rocket
package freechips.rocketchip.rocket
import Chisel._
import Chisel.ImplicitConversions._
import config._
import diplomacy._
import uncore.constants._
import uncore.tilelink2._
import uncore.util._
import util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
trait HasMissInfo extends HasL1HellaCacheParameters {
val tag_match = Bool()