riscv/rocket-chip
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)

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* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
This commit is contained in:
Henry Cook
2017-07-07 10:48:16 -07:00
committed by GitHub
parent c28c23150d
commit 4c595d175c
238 changed files with 1347 additions and 10978 deletions
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9
src/main/scala/rocket/Instructions.scala
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@ -1,9 +1,10 @@
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package rocket
package freechips.rocketchip.rocket
import Chisel._
import scala.collection.mutable.ArrayBuffer
/* Automatically generated by parse-opcodes */
object Instructions {
@ -231,7 +232,7 @@ object Causes {
val load_page_fault = 0xd
val store_page_fault = 0xf
val all = {
val res = collection.mutable.ArrayBuffer[Int]()
val res = ArrayBuffer[Int]()
res += misaligned_fetch
res += fetch_access
res += illegal_instruction
@ -463,7 +464,7 @@ object CSRs {
val mhpmcounter30h = 0xb9e
val mhpmcounter31h = 0xb9f
val all = {
val res = collection.mutable.ArrayBuffer[Int]()
val res = ArrayBuffer[Int]()
res += fflags
res += frm
res += fcsr
@ -615,7 +616,7 @@ object CSRs {
res.toArray
}
val all32 = {
val res = collection.mutable.ArrayBuffer(all:_*)
val res = ArrayBuffer(all:_*)
res += cycleh
res += timeh
res += instreth