Refactor package hierarchy and remove legacy bus protocol implementations (#845)
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
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@ -1,15 +1,14 @@
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// See LICENSE.SiFive for license details.
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package rocket
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package freechips.rocketchip.rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import config._
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import diplomacy._
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import uncore.constants._
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import uncore.tilelink2._
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import uncore.util._
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import util._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.coreplex.{RationalCrossing, RocketCrossing, RocketTilesKey}
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import freechips.rocketchip.diplomacy.AddressSet
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import TLMessages._
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class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
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@ -83,8 +82,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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dataArb.io.out.ready := true
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metaArb.io.out.ready := true
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val rational = p(coreplex.RocketCrossing) match {
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case coreplex.RationalCrossing(_) => true
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val rational = p(RocketCrossing) match {
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case RationalCrossing(_) => true
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case _ => false
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}
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@ -160,7 +159,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val s1_victim_way = Wire(init = replacer.way)
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val (s1_hit_way, s1_hit_state, s1_meta, s1_victim_meta) =
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if (usingDataScratchpad) {
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val baseAddr = GetPropertyByHartId(p(coreplex.RocketTilesKey), _.dcache.flatMap(_.scratch.map(_.U)), io.hartid)
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val baseAddr = GetPropertyByHartId(p(RocketTilesKey), _.dcache.flatMap(_.scratch.map(_.U)), io.hartid)
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val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + nSets * cacheBlockBytes
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val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset)
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val dummyMeta = L1Metadata(UInt(0), ClientMetadata.onReset)
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