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Refactor package hierarchy and remove legacy bus protocol implementations (#845)

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* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
This commit is contained in:
Henry Cook
2017-07-07 10:48:16 -07:00
committed by GitHub
parent c28c23150d
commit 4c595d175c
238 changed files with 1347 additions and 10978 deletions
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5
src/main/scala/regmapper/RegisterCrossing.scala
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@ -1,10 +1,11 @@
// See LICENSE.SiFive for license details.
package regmapper
package freechips.rocketchip.regmapper
import Chisel._
import chisel3.util.{Irrevocable}
import util.{AsyncQueue,AsyncResetRegVec}
import freechips.rocketchip.util.{AsyncQueue,AsyncResetRegVec}
// A very simple flow control state machine, run in the specified clock domain
class BusyRegisterCrossing extends Module {