Refactor package hierarchy and remove legacy bus protocol implementations (#845)

* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package

src/main/scala/regmapper/RegField.scala

@@ -1,10 +1,11 @@
 // See LICENSE.SiFive for license details.
 
-package regmapper
+package freechips.rocketchip.regmapper
 
 import Chisel._
 import chisel3.util.{ReadyValidIO}
-import util.{SimpleRegIO}
+
+import freechips.rocketchip.util.{SimpleRegIO}
 
 case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt))
 object RegReadFn

src/main/scala/regmapper/RegMapper.scala

@@ -1,10 +1,11 @@
 // See LICENSE.SiFive for license details.
 
-package regmapper
+package freechips.rocketchip.regmapper
 
 import Chisel._
-import diplomacy._
-import util.{GenericParameterizedBundle}
+
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.util.{GenericParameterizedBundle, ReduceOthers}
 
 // A bus agnostic register interface to a register-based device
 
@@ -154,7 +155,7 @@ object RegMapper
     def mux(valid: Bool, select: Seq[Bool], guard: Seq[Bool], flow: Seq[Seq[(Bool, Bool)]]): Vec[Bool] =
       Vec(((select zip guard) zip flow).map { case ((s, g), f) =>
         val out = Wire(Bool())
-        util.ReduceOthers((out, valid && s && g) +: f)
+        ReduceOthers((out, valid && s && g) +: f)
         out || !g
       })
 

src/main/scala/regmapper/RegisterCrossing.scala

@@ -1,10 +1,11 @@
 // See LICENSE.SiFive for license details.
 
-package regmapper
+package freechips.rocketchip.regmapper
 
 import Chisel._
 import chisel3.util.{Irrevocable}
-import util.{AsyncQueue,AsyncResetRegVec}
+
+import freechips.rocketchip.util.{AsyncQueue,AsyncResetRegVec}
 
 // A very simple flow control state machine, run in the specified clock domain
 class BusyRegisterCrossing extends Module {