riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

Browse Source 
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
This commit is contained in:
Henry Cook
2017-07-07 10:48:16 -07:00
committed by GitHub
parent c28c23150d
commit 4c595d175c
238 changed files with 1347 additions and 10978 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/jtag/JtagShifter.scala
View File

@ -1,6 +1,6 @@
// See LICENSE.jtag for license details.
package jtag
package freechips.rocketchip.jtag
import chisel3._
import chisel3.core.DataMirror

4
src/main/scala/jtag/JtagStateMachine.scala
View File

@ -1,10 +1,10 @@
// See LICENSE.jtag for license details.
package jtag
package freechips.rocketchip.jtag
import util.{AsyncResetRegVec}
import chisel3._
import chisel3.util._
import freechips.rocketchip.util.{AsyncResetRegVec}
object JtagState {
sealed abstract class State(val id: Int) {

2
src/main/scala/jtag/JtagTap.scala
View File

@ -1,6 +1,6 @@
// See LICENSE.jtag for license details.
package jtag
package freechips.rocketchip.jtag
import chisel3._
import chisel3.util._

2
src/main/scala/jtag/JtagUtils.scala
View File

@ -1,6 +1,6 @@
// See LICENSE.jtag for license details.
package jtag
package freechips.rocketchip.jtag
import chisel3._
import chisel3.util._

2
src/main/scala/jtag/Utils.scala
View File

@ -1,6 +1,6 @@
// See LICENSE.jtag for license details.
package jtag
package freechips.rocketchip.jtag
import chisel3._
import chisel3.util._

2
src/main/scala/jtag/package.scala
View File

@ -1,5 +1,7 @@
// See LICENSE.jtag for license details
package freechips.rocketchip
import scala.language.implicitConversions
package object jtag {