Refactor package hierarchy and remove legacy bus protocol implementations (#845)
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
This commit is contained in:
Henry Cook
GitHub
@ -1,161 +1,40 @@
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// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package groundtest
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package freechips.rocketchip.groundtest
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import Chisel._
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import rocket._
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import diplomacy._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.util._
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import tile.TileKey
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import junctions._
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import config._
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import coreplex._
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import rocketchip._
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import freechips.rocketchip.chip.{BaseConfig, ExtMem}
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import freechips.rocketchip.config.Config
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import freechips.rocketchip.coreplex.{CacheBlockBytes, L1toL2Config, WithBufferlessBroadcastHub}
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import freechips.rocketchip.rocket.{DCacheParams, PAddrBits}
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import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
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/** Actual testing target Configs */
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class GroundTestConfig extends Config(new WithGroundTestTiles ++ new BaseConfig)
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class TraceGenConfig extends Config(new WithTraceGen(List.fill(2){ DCacheParams(nSets = 16, nWays = 1) }) ++ new BaseConfig)
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class ComparatorConfig extends Config(
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new WithComparator(1) ++ new GroundTestConfig)
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class ComparatorL2Config extends Config(
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new WithAtomics ++ new WithPrefetches ++
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new WithL2Cache ++ new ComparatorConfig)
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class ComparatorBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new ComparatorConfig)
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class ComparatorStatelessConfig extends Config(
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new WithStatelessBridge ++ new ComparatorConfig)
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class MemtestConfig extends Config(new WithMemtest(1) ++ new GroundTestConfig)
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class MemtestL2Config extends Config(
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new WithL2Cache ++ new MemtestConfig)
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class MemtestBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new MemtestConfig)
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class MemtestStatelessConfig extends Config(
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new WithStatelessBridge ++ new MemtestConfig)
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// Test ALL the things
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class FancyMemtestConfig extends Config(
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new WithMemtest(2) ++
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
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new WithL2Cache ++ new GroundTestConfig)
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class CacheFillTestConfig extends Config(
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new WithNL2Ways(4) ++ new WithL2Capacity(4) ++
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new WithCacheFillTest(1) ++ new WithL2Cache ++ new GroundTestConfig)
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class BroadcastRegressionTestConfig extends Config(
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new WithBroadcastRegressionTest(1) ++ new GroundTestConfig)
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class BufferlessRegressionTestConfig extends Config(
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new WithBufferlessBroadcastHub ++ new BroadcastRegressionTestConfig)
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class CacheRegressionTestConfig extends Config(
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new WithCacheRegressionTest(1) ++ new WithL2Cache ++ new GroundTestConfig)
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class TraceGenConfig extends Config(
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new WithTraceGen(2) ++ new GroundTestConfig)
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class TraceGenBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new TraceGenConfig)
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class TraceGenL2Config extends Config(
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new WithNL2Ways(1) ++ new WithL2Capacity(32 * 64 / 1024) ++
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new WithL2Cache ++ new TraceGenConfig)
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class Edge128BitComparatorConfig extends Config(
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new WithEdgeDataBits(128) ++ new ComparatorConfig)
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class Edge128BitMemtestConfig extends Config(
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new WithEdgeDataBits(128) ++ new MemtestConfig)
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class Edge32BitComparatorConfig extends Config(
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new WithEdgeDataBits(32) ++ new ComparatorL2Config)
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class Edge32BitMemtestConfig extends Config(
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new WithEdgeDataBits(32) ++ new MemtestConfig)
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class TraceGenBufferlessConfig extends Config(new WithBufferlessBroadcastHub ++ new TraceGenConfig)
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/* Composable Configs to set individual parameters */
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class WithGroundTestTiles extends Config((site, here, up) => {
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case TileKey => site(GroundTestKey).head
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case NTiles => site(GroundTestKey).size
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})
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class WithComparator(n: Int) extends Config((site, here, up) => {
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case GroundTestKey => Seq.fill(n) {
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GroundTestTileParams(uncached = 2, dcache = None)
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}
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case BuildGroundTest =>
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(p: Parameters) => Module(new ComparatorCore()(p))
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case ComparatorKey => ComparatorParameters(
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targets = Seq(site(ExtMem).base, testRamAddr),
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width = 8,
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operations = 1000,
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atomics = false,
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prefetches = false)
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})
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class WithAtomics extends Config((site, here, up) => {
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case ComparatorKey => up(ComparatorKey, site).copy(atomics = true)
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})
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class WithPrefetches extends Config((site, here, up) => {
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case ComparatorKey => up(ComparatorKey, site).copy(prefetches = true)
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})
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class WithMemtest(n: Int) extends Config((site, here, up) => {
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case GroundTestKey => Seq.fill(n) {
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GroundTestTileParams(uncached = 1)
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}
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case GeneratorKey => TrafficGeneratorParameters(
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maxRequests = 128,
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startAddress = BigInt(site(ExtMem).base))
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case BuildGroundTest =>
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(p: Parameters) => Module(new GeneratorTest()(p))
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})
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class WithCacheFillTest(n: Int) extends Config((site, here, up) => {
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case GroundTestKey => Seq.fill(n) {
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GroundTestTileParams(uncached = 1, dcache = None)
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}
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case BuildGroundTest =>
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(p: Parameters) => Module(new CacheFillTest()(p))
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})
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class WithBroadcastRegressionTest(n: Int) extends Config((site, here, up) => {
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case GroundTestKey => Seq.fill(n) {
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GroundTestTileParams(uncached = 1, maxXacts = 3)
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}
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case BuildGroundTest =>
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(p: Parameters) => Module(new RegressionTest()(p))
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case GroundTestRegressions =>
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(p: Parameters) => RegressionTests.broadcastRegressions(p)
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})
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class WithCacheRegressionTest(n: Int) extends Config((site, here, up) => {
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case GroundTestKey => Seq.fill(n) {
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GroundTestTileParams(uncached = 1, maxXacts = 5)
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}
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case BuildGroundTest =>
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(p: Parameters) => Module(new RegressionTest()(p))
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case GroundTestRegressions =>
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(p: Parameters) => RegressionTests.cacheRegressions(p)
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})
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class WithTraceGen(n: Int) extends Config((site, here, up) => {
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case GroundTestKey => Seq.fill(n) {
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GroundTestTileParams(dcache = Some(DCacheParams(nSets = 16, nWays = 1)))
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}
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case BuildGroundTest =>
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(p: Parameters) => Module(new GroundTestTraceGenerator()(p))
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case GeneratorKey => TrafficGeneratorParameters(
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maxRequests = 8192,
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startAddress = 0)
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case AddressBag => {
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val nSets = 2
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val nWays = 1
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val blockOffset = site(CacheBlockOffsetBits)
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val nBeats = site(CacheBlockBytes)/site(L1toL2Config).beatBytes
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List.tabulate(4 * nWays) { i =>
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Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
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}.flatten
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}
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class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config((site, here, up) => {
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case GroundTestTilesKey => params.map { dcp => TraceGenParams(
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dcache = Some(dcp),
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wordBits = site(XLen),
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addrBits = site(PAddrBits),
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addrBag = {
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val nSets = 2
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val nWays = 1
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val blockOffset = log2Up(site(CacheBlockBytes))
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val nBeats = site(CacheBlockBytes)/site(L1toL2Config).beatBytes
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List.tabulate(4 * nWays) { i =>
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Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
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}.flatten
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},
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maxRequests = nReqs,
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memStart = site(ExtMem).base,
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numGens = params.size)
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}
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case MaxHartIdBits => log2Up(params.size)
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})
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