riscv/rocket-chip
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)

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* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
This commit is contained in:
Henry Cook authored and GitHub committed 2017-07-07 10:48:16 -07:00
1 parent c28c23150d
commit 4c595d175c
238 files changed
+1347 -10978
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src/main/scala/coreplex/BaseCoreplex.scala
+7 -7
View File
@@ -1,14 +1,14 @@
// See LICENSE.SiFive for license details.
package coreplex
package freechips.rocketchip.coreplex
import Chisel._
import config._
import diplomacy._
import tile.XLen
import tile.TileInterrupts
import uncore.tilelink2._
import util._
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile.{ XLen, TileInterrupts}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
/** Widths of various points in the SoC */
case class TLBusConfig(beatBytes: Int)